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| data sheet, v1.0, apr. 2008 microcontrollers TC1796 32-bit single-chip microcontroller tricore www.datasheet.co.kr datasheet pdf - http://www..net/
edition 2008-04 published by infineon technologies ag 81726 munich, germany ? 2008 infineon technologies ag all rights reserved. legal disclaimer the information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, infineon technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. information for further information on technology, delivery terms an d conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact the nearest infineon technologies office. infineon technologies components may be used in life -support devices or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or ef fectiveness of that device or system. life support devices or systems are intended to be implanted in the hu man body or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered. www.datasheet.co.kr datasheet pdf - http://www..net/ data sheet, v1.0, apr. 2008 microcontrollers TC1796 32-bit single-chip microcontroller tricore www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 data sheet v1.0, 2008-04 trademarks tricore? is a trademark of infineon technologies ag. TC1796 data sheet revision history: v1.0, 2008-04 previous version: v1.0, 2008-04 ?preliminary? page subjects (major changes since last revision) ?preliminary? status removed. no changes in content. changes from v0.7, 2006-03 to v1.0, 2008-04 preliminary 32 the list of not connected pins (n.c.) improved by adding several formerly as v ss labeled pins. 69 watchdog timer, double reset detection, description corrected. 80 rtid register updated for the design step be. 85 the description of the inactive device current improved. 96 adc parameters sample and conversion time moved to a dedicated table. 107 the description of the power supply sequence improved.. 115 bfclko clock, duty cycle description extended. 126 mli timing, maximum operating frequency limit extended, t31 added. 131 the drawing of the package updated. green package variant included. 133 example of a temperature profile corrected. we listen to your comments any information within this document that you feel is wrong, unclear or missing at all? your feedback will help us to continuously improve the quality of this document. please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 table of contents data sheet 5 v1.0, 2008-04 table of contents 1 summary of features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 general device information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 TC1796 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.4 pad driver and input classes overview . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.5 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.5.1 pull-up/pull-down behavior of the pins . . . . . . . . . . . . . . . . . . . . . . . . 35 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.1 system architecture and on-chip bus systems . . . . . . . . . . . . . . . . . . . . 36 3.2 on-chip memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.3 architectural address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.4 memory protection system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.5 external bus unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.6 peripheral control processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.7 dma controller and memory checker . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.8 interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.9 asynchronous/synchronous serial interfaces (asc0, asc1) . . . . . . . . . . 48 3.10 high-speed synchronous serial interfaces (ssc0, ssc1) . . . . . . . . . . . . 50 3.11 micro second bus interfaces (msc0, msc1) . . . . . . . . . . . . . . . . . . . . . . 52 3.12 multican controller (can) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.13 micro link serial bus interface (mli0, mli1) . . . . . . . . . . . . . . . . . . . . . . . 57 3.14 general purpose timer array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.14.1 functionality of gpta0/gpta1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3.14.2 functionality of ltca2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 3.15 analog-to-digital converter (adc0, adc1) . . . . . . . . . . . . . . . . . . . . . . . . 63 3.16 fast analog-to-digital converter unit (fadc) . . . . . . . . . . . . . . . . . . . . . . 65 3.17 system timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 3.18 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 3.19 system control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 3.20 boot options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 3.21 power management system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 3.22 on-chip debug support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 3.23 clock generation and pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 3.24 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 3.25 identification register values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 4 electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 4.1 general parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 4.1.1 parameter interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 table of contents data sheet 6 v1.0, 2008-04 4.1.2 pad driver and pad classes summary . . . . . . . . . . . . . . . . . . . . . . . . . 83 4.1.3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 4.1.4 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 4.2 dc parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 4.2.1 input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 4.2.2 analog to digital converters (adc0/adc1) . . . . . . . . . . . . . . . . . . . . . 92 4.2.3 fast analog to digital converter (fadc) . . . . . . . . . . . . . . . . . . . . . . . . 99 4.2.4 oscillator pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 4.2.5 temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 4.2.6 power supply current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 4.3 ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 4.3.1 testing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 4.3.2 output rise/fall times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 4.3.3 power sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 4.3.4 power, pad and reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 4.3.5 phase locked loop (pll) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 4.3.6 bfclko output clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 4.3.7 debug trace timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 4.3.8 jtag interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 4.3.9 ebu demultiplexed timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 4.3.9.1 demultiplexed read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 4.3.9.2 demultiplexed write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 4.3.10 ebu burst mode read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 4.3.11 ebu arbitration signal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 4.3.12 peripheral timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 4.3.12.1 micro link interface (mli) timing . . . . . . . . . . . . . . . . . . . . . . . . . . 126 4.3.12.2 micro second channel (msc) interface timing . . . . . . . . . . . . . . . 128 4.3.12.3 synchronous serial channel (ssc) master mode timing . . . . . . . . 129 5 package and reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 5.1 package parameters (p/pg-bga-416-4) . . . . . . . . . . . . . . . . . . . . . . . . 130 5.2 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 5.3 flash memory parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 5.4 quality declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 summary of features data sheet 7 v1.0, 2008-04 1 summary of features ? high-performance 32-bit super-scalar tricore v1.3 cpu with 4-stage pipeline ? superior real-time performance ? strong bit handling ? fully integrated dsp capabilities ? single precision floating point unit (fpu) ? 150 mhz operation at full temperature range ? 32-bit peripheral control processor with single cycle instruction (pcp2) ? 16 kbyte parameter memory (pram) ? 32 kbyte code memory (cmem) ? multiple on-chip memories ? 2 mbyte program flash memory (pflash) with ecc ? 128 kbyte data flash memory (dflash) usable for eeprom emulation ? 136 kbyte data memory (ldram, sram, sbram) ? 8 kbyte dual-ported memory (dpram) ? 48 kbyte code scratchpad memory (spram) ? 16 kbyte instruction cache (icache) ? 16 kbyte bootrom (brom) ? 16-channel dma controller ? 32-bit external bus interface unit (ebu) with ? 75 dedicated address/data bus, clock, and control lines ? synchronous burst flash access capability ? sophisticated interrupt system with 2 255 hardware priority arbitration levels serviced by cpu or pcp2 ? high performing on-chip bus structure ? two 64-bit local memory buses between ebu, flash and data memory ? 32-bit system peripheral bus (spb) for on-chip peripheral and functional units ? 32-bit remote peripheral bus (rpb) for high-speed on-chip peripheral units ? two bus bridges (lfi bridge, dma controller) ? peripheral control processor with single cycle instruction (pcp2) ? 16 kbyte parameter memory (pram) ? 32 kbyte code memory (cmem) ? versatile on-chip peripheral units ? two asynchronous/synchronous serial channels (asc) with baud rate generator, parity, framing and overrun error detection ? two high-speed synchronous serial channels (ssc) with programmable data length and shift direction ? two serial micro second bus interfaces (msc) for serial port expansion to external power devices ? two high-speed micro link interfaces (mli) for serial inter-processor communication www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 summary of features data sheet 8 v1.0, 2008-04 ? one multican module with four can nodes and 128 free assignable message objects for high efficiency data handling via fifo buffering and gateway data transfer (one can node supports ttcan functionality) ? two general purpose timer array modules (gpta) with additional local timer cell array (ltca2) providing a powerful set of digital signal filtering and timer functionality to realize autonomous and complex input/output management ? two 16-channel analog-to-digital converter units (adc) with selectable 8-bit, 10- bit, or 12-bit resolution ? one 4-channel fast analog-to-digital converter unit (fadc) with concatenated comb filters for hardware data reduction: supporting 10-bit resolution, min. conversion time of 280ns ? 44 analog input lines for adc and fadc ? 123 digital general purpose i/o lines, 4 input lines ? digital i/o ports with 3.3 v capability ? on-chip debug support for ocds level 1 and 2 (cpu, pcp3, dma) ? dedicated emulation device chip for multi-core debugging, tracing, and calibration via usb v1.1 interface available (TC1796ed) ? power management system ? clock generation unit with pll ? core supply voltage of 1.5 v ? i/o voltage of 3.3 v ? full automotive temperature range: -40 to +125c ? p/pg-bga-416-4 package www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 summary of features data sheet 9 v1.0, 2008-04 ordering information the ordering code for infineon microcontrolle rs provides an exact reference to the required product. this ordering code identifies: ? the derivative itself, i.e. its function set, the temperature range, and the supply voltage ? the package and the type of delivery. for the available ordering codes for the TC1796 please refer to the ?product catalog microcontrollers? , which summarizes all available microcontroller variants. this document describes the derivatives of the device.the table 1 enumerates these derivatives and summarizes the differences. table 1 TC1796 derivative synopsis derivative ambient temperature range sak-TC1796-256f150e t a = -40 o c to +125 o c www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 general device information data sheet 10 v1.0, 2008-04 2 general device information 2.1 TC1796 block diagram figure 1 TC1796 block diagram fpu tri core (tc1m) pmi 48 kb spram 16 kb icache ocds debug interface /jtag asc0 asc1 gpta1 ltca2 fpi-bus interface 16 kb pram pcp2 core 32 kb cmem interrupts mli 1 f cpu f fpi system peripheral bus remote peripheral bus ports scu ssc1 ssc0 mcb05573_mod multican (with 4 can nodes) stm spram: icache: ldram dpram: brom: pflash: dflash: sbram: sram: pram: cmem: plmb: dlmb: rpb: spb: shaded: dma bi0 bi1 smif dmi 56 kb ldram 8 kb dpram cps ebu scratch-pad ram instruction cache local data ram dual-port ram boot rom program flash memory data flash memory stand-by data memory data memory pcp parameter memory pcp code memory program local memory bus data local memory bus remote peripheral bus system peripheral bus only available in tc 1796ed gpta0 adc0 adc1 lfi bridge program local memory bus data local memory bus dbcu dmu 64 kb sram 16 kb sbram p lmb d lmb rpb spb fadc analog input assignment rbcu mem chk msc 0 msc 1 mli 0 pbcu pmu 16 kb brom 2 mb pflash 128 kb dflash emulation memory interface sbcu pll lmi www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 general device information data sheet 11 v1.0, 2008-04 2.2 logic symbol figure 2 TC1796 logic symbol mca05583_mod alternate functions : bypass nmi porst hdrst testmode general control xtal2 xtal1 oscillator tms tdo tdi tck jtag / ocds brkout brkin trst v ss v dd 13 62 digital circuitry power supply v ddp 11 v ddfl3 v d d sbram TC1796 v faref v fagnd v ddmf v ssmf fadc analog power supply v ar efx v agnd x v ddm v ssm adc0 /adc1 analog power supply an[43:0] adc analog inputs port 0 port 1 port 2 port 4 port 5 port 3 gpta ssc0 / ssc1 / gpta d[31:0] a[23:0] chip select external bus unit interface control bfclki bflcko port 6 port 7 port 8 port 9 port 10 mli0 / scu asc0 / asc1 / msc0 / msc1 /mli0 asc0 / asc1 / ssc1 / can adc0 / adc1 mli 1 / gpta msc0 / msc1 / gpta hwcfg 2 v ddaf v ssaf v ddebu 9 v ddosc v ddosc3 2 n.c. 10 tstres tr[15:0] trclk 8 dedicated ssc0 i/o lines lvds msc outputs v ssosc 2 6 4 9 8 8 12 8 16 16 14 16 16 13 5 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 general device information data sheet 12 v1.0, 2008-04 2.3 pin configuration figure 3 TC1796 pinning for p/pg-bga-416-4 package (top view) mca0558 4 v agnd1 v aref1 mtsr 0 v dd v ddm v ssm rd adv bc0 bc1 bc2 bc3 baa cs0 cs1 cs2 cs3 bf clki po rst nmi hd rst v ss v agnd0 v aref0 1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526 p2.9 p2.6 p2.13 p2.15 p2.14 p2.12 p2.11 p2.10 p2.7 p2.5 p2.8 p2.2 p2.4 p2.3 p0.15 a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af a b c d e f g h j k l m n p r t u v w y a a a b a c a d a e a f 1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526 an22 an21 an19 an16 an23 an20 an17 an13 an18 an14 an10 an15 an11 an5 an2 an12 an9 an3 an7 an8 an4 an32 an38 an6 an1 an34 an40 an0 an33 an36 an41 an37 an39 an43 an42 an35 an28 an29 an26 an27 an24 an25 an30 an31 v fagnd v faref v dd v ss v ddp p6.9 p6.8 p6.5 p1.11 p1.5 p1.12 p1.4 v dd v ss p7.2 v dd v ss v dd v ddp v ddp v ss v dd v ss v ddp v ss v dd v ddp v ss v dd v ddp v ss v dd v ddp v ddebu n.c. v ddebu v ddebu v ddebu v ddebu v ss v dd v dd v ddebu v ddebu v dd v ss n.c. d26 d29 d30 d24 d27 d31 d23 d25 d28 d15 d20 d21 d11 d17 d22 d10 d14 d18 d7 d12 d16 d4 d8 d13 d2 d5 d9 d0 d3 d1 d6 d19 v ss a0 a1 a2 a21 a23 a22 a19 a20 a18 a16 a17 a14 a12 a11 a10 a13 a7 a8 a6 a3 a4 a9 a5 a15 v ss brk out tdo tck tdi trst brk in tms xtal 2 xtal 1 tst res v ss osc v dd osc v dd osc3 p0.14 p0.9 p0.5 p0.6 p0.2 p0.4 p0.8 p0.1 p0.3 p0.7 p0.12 p0.10 p0.13 p0.11 p0.0 p3.15 p3.7 p3.14 p3.6 p3.10 p3.8 p3.9 p3.12 p3.4 p3.13 p3.11 p3.2 p3.5 p3.3 p3.1 p3.0 p5.1 p5.0 p5.2 p5.3 p5.7 p5.6 p5.5 p5.4 so n1 so p1a so p0a fcl p1a fcl n1 fcl n0 v ddfl3 v ddfl3 fcl p0a so n0 p9.4 p9.5 p9.6 p9.1 p9.0 p9.7 p9.8 p9.2 p9.3 p10.3 p10.2 p10.1 p10.0 by pass p6.12 p6.11 p6.6 p6.14 p6.10 p6.4 p6.15 p6.13 p6.7 p8.1 p8.0 p8.4 p8.3 p8.7 p8.5 p8.2 p8.6 p1.15 p1.14 p1.13 p1.10 p1.9 p1.8 p1.3 p1.7 p1.6 p1.2 p1.1 p1.0 v dd sbram p7.6 p7.1 p7.0 p7.4 p7.3 p7.7 p7.5 v ssmf v ddmf v ssaf v ddaf p4.4 p4.8 p4.3 p4.12 p4.15 p4.11 p4.13 p4.2 p4.10 p4.7 p4.5 p4.14 p4.6 p4.9 p4.0 p4.1 mrst 0 slso 1 slso 0 sclk 0 v ddp v ddp v ddp v ddp v ss v ss v ddebu v dd v ddebu slsi0 hlda hold mr/w rd/ wr wait n.c. n.c. n.c. n.c. breq bf clko v ss v ss v ss v ss v ss v ss tr1 tr0 n.c. n.c. n.c. n.c. cs comb tr3 tr2 tr4 tr5 tr6 tr7 tr clk tr8 tr9 tr10 tr11 tr12 tr13 tr14 tr15 test mode v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 general device information data sheet 13 v1.0, 2008-04 2.4 pad driver and input classes overview the TC1796 provides different types and classes of input and output lines. for understanding of the abbreviations in table 2 starting at the next page, table 4 gives an overview on the pad type and class types. 2.5 pin definitions and functions www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 general device information data sheet 14 v1.0, 2008-04 table 2 pin definitions and functions symbol pins i/o pad class power supply functions external bus interface lines (ebu) d[31:0] d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d16 d17 d18 d19 d20 d21 d22 d23 d24 d25 d26 d27 d28 d29 d30 d31 t26 t24 u26 t25 v26 u25 u23 w26 v25 u24 y26 aa26 w25 v24 y25 ab26 w24 aa25 y24 aa23 ab25 ab24 aa24 ac26 ad26 ac25 ae26 ad25 ac24 ae25 ae24 ad24 i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o b1 v ddebu ebu data bus lines the ebu data bus lines d[31:0] serve as external data bus. data bus line 0 data bus line 1 data bus line 2 data bus line 3 data bus line 4 data bus line 5 data bus line 6 data bus line 7 data bus line 8 data bus line 9 data bus line 10 data bus line 11 data bus line 12 data bus line 13 data bus line 14 data bus line 15 data bus line 16 data bus line 17 data bus line 18 data bus line 19 data bus line 20 data bus line 21 data bus line 22 data bus line 23 data bus line 24 data bus line 25 data bus line 26 data bus line 27 data bus line 28 data bus line 29 data bus line 30 data bus line 31 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 general device information data sheet 15 v1.0, 2008-04 a[23:0] a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 a20 a21 a22 a23 j24 j25 j26 k25 k26 j23 k24 l25 l26 k23 m26 m25 m24 l24 n26 n23 n24 n25 p26 p24 p25 r24 r26 r25 o o o o o o o o o o o o o o o o o o o o o o o o o b1 v ddebu ebu address bus lines a[23:0] the ebu address bus lines serve as external address bus. address bus line 0 address bus line 1 address bus line 2 address bus line 3 address bus line 4 address bus line 5 address bus line 6 address bus line 7 address bus line 8 address bus line 9 address bus line 10 address bus line 11 address bus line 12 address bus line 13 address bus line 14 address bus line 15 address bus line 16 address bus line 17 address bus line 18 address bus line 19 address bus line 20 address bus line 21 address bus line 22 address bus line 23 cs0 cs1 cs2 cs3 ae21 ad21 ad20 ad19 o o o o b1 v ddebu chip select output lines chip select output line 0 chip select output line 1 chip select output line 2 chip select output line 3 cs comb ae19 o b1 v ddebu combined chip select output for global select / emulator memory region/emulator overlay memory table 2 pin definitions and functions (cont?d) symbol pins i/o pad class power supply functions www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 general device information data sheet 16 v1.0, 2008-04 bfclko af25 o b2 v ddebu burst mode flash clock output (non- differential) bfclki af24 i b1 burst mode flash clock input (feedback clock) rd af20 o b1 read control line rd/ wr af21 o b1 write control line adv af22 o b1 address valid output mr/ w af19 o b1 motorola-style read/write control signal bc0 bc1 bc2 bc3 ae17 ad17 af18 ae18 o o o o b1 byte control lines byte control line 0 byte control line 1 byte control line 2 byte control line 3 wait ae20 i b1 wait input for inserting wait-states baa af23 o b1 burst address advance output hold af17 i b1 hold request input hlda ad18 o b1 hold acknowledge output breq ad22 o b1 bus request output table 2 pin definitions and functions (cont?d) symbol pins i/o pad class power supply functions www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 general device information data sheet 17 v1.0, 2008-04 parallel ports p0 i/o a1 v ddp port 0 port 0 is a 16-bit bidirectional general- purpose i/o port. p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 p0.8 p0.9 p0.10 p0.11 p0.12 p0.13 p0.14 p0.15 a9 a8 a7 b8 b7 a6 b6 c8 c7 b5 c6 d6 c5 d5 a5 d4 i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o port 0 i/o line 0 port 0 i/o line 1 port 0 i/o line 2 port 0 i/o line 3 port 0 i/o line 4 port 0 i/o line 5 port 0 i/o line 6 port 0 i/o line 7 port 0 i/o line 8 port 0 i/o line 9 port 0 i/o line 10 port 0 i/o line 11 port 0 i/o line 12 port 0 i/o line 13 port 0 i/o line 14 port 0 i/o line 15 the states of the port 0 pins are latched into the software configuration input register scu_scilr at the rising edge of hdrst . therefore, port 0 pins can be used for operating mode selections by software. table 2 pin definitions and functions (cont?d) symbol pins i/o pad class power supply functions www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 general device information data sheet 18 v1.0, 2008-04 p1 i/o a1/a2 v ddp port 1 port 1 is a 16-bit bi-directional general- purpose i/o port which can be alternatively used for the mli0 interface or as external trigger input lines. p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 p1.8 p1.9 p1.10 p1.11 p1.12 p1.13 p1.14 p1.15 p3 p2 p1 n1 n4 m4 n3 n2 m3 m2 m1 l4 p4 l3 l2 l1 i i i i i o i o o i o i i o i i i a1 a1 a1 a1 a1 a2 a1 a2 a2 a1 a2 a1 a1 a2 a1 a1 a1 req0 req1 req2 req3 tready0b tclk0 tready0a tvalid0a tdata0 rclk0a rready0a rvalid0a rdata0a sysclk rclk0b rvalid0b rdata0b external trigger input 0 external trigger input 1 external trigger input 3 external trigger input 2 mli0 transmit channel ready input b mli0 transmit channel clock output mli0 transmit channel ready input a mli0 transmit channel valid output a mli0 transmit channel data output mli0 receive channel clock input a mli0 receive channel ready output a mli0 receive channel valid input a mli0 receive channel data input a system clock output mli0 receive channel clock input b mli0 receive channel valid input b mli0 receive channel data input b table 2 pin definitions and functions (cont?d) symbol pins i/o pad class power supply functions www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 general device information data sheet 19 v1.0, 2008-04 p2 i/o a1/a2 v ddp port 2 port 2 is a 14-bit bi-directional general- purpose i/o port which can be used alternatively for the six upper ssc slave select outputs or for gpta i/o lines. p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 d3 d2 d1 c1 b1 b2 o o o o o o a2 a2 a2 a2 a2 a2 slso2 slso3 slso4 slso5 slso6 slso7 slave select output line 2 slave select output line 3 slave select output line 4 slave select output line 5 slave select output line 6 slave select output line 7 p2.8 p2.9 p2.10 p2.11 p2.12 p2.13 p2.14 p2.15 c2 a2 b3 c3 c4 a3 b4 a4 i/o i/o i/o i/o i/o i/o i/o i/o a1 a1 a1 a1 a1 a1 a1 a1 in0 / out0 line of gpta in1 / out1 line of gpta in2 / out2 line of gpta in3 / out3 line of gpta in4 / out4 line of gpta in5 / out5 line of gpta in6 / out6 line of gpta in7 / out7 line of gpta table 2 pin definitions and functions (cont?d) symbol pins i/o pad class power supply functions www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 general device information data sheet 20 v1.0, 2008-04 p3 i/o a1 v ddp port 3 port 3 is a 16-bit bi-directional general- purpose i/o port which can be alternatively used for gpta i/o lines. p3.0 p3.1 p3.2 p3.3 p3.4 p3.5 p3.6 p3.7 p3.9 p3.8 p3.10 p3.11 p3.12 p3.13 p3.14 p3.15. b12 a12 c13 b11 c12 a11 b10 c9 d10 c11 c10 d13 d11 d12 a10 b9 in8 / out8 line of gpta in9 / out9 line of gpta in10 / out10 line of gpta in11 / out11 line of gpta in12 / out12 line of gpta in13 / out13 line of gpta in14 / out14 line of gpta in15 / out15 line of gpta in16 / out16 line of gpta in17 / out17 line of gpta in18 / out18 line of gpta in19 / out19 line of gpta in20 / out20 line of gpta in21 / out21 line of gpta in22 / out22 line of gpta in23 / out23 line of gpta table 2 pin definitions and functions (cont?d) symbol pins i/o pad class power supply functions www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 general device information data sheet 21 v1.0, 2008-04 p4 i/o a1/a2 v ddp port 4 port 4 is a 16-bit bi-directional general- purpose i/o port which can be alternatively used for gpta i/o lines. p4.0 p4.1 p4.2 p4.3 p4.4 p4.5 p4.6 p4.7 p4.8 p4.9 p4.10 p4.11 p4.12 p4.13 p4.14 p4.15 ad10 ae10 ad11 ae11 ac12 ad12 af10 ae12 ac13 af11 af12 ad13 ac14 ae13 af13 ad14 i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o a2 1) a2 1) a2 1) a2 1) a2 1) a2 1) a2 1) a2 1) a1 a1 a1 a1 a1 a1 a1 a1 in24 / out24 line of gpta in25 / out25 line of gpta in26 / out26 line of gpta in27 / out27 line of gpta in28 / out28 line of gpta in29 / out29 line of gpta in30 / out30 line of gpta in31 / out31 line of gpta in32 / out32 line of gpta in33 / out33 line of gpta in34 / out34 line of gpta in35 / out35 line of gpta in36 / out36 line of gpta in37 / out37 line of gpta in38 / out38 line of gpta in39 / out39 line of gpta table 2 pin definitions and functions (cont?d) symbol pins i/o pad class power supply functions www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 general device information data sheet 22 v1.0, 2008-04 p5 i/o a2 v ddp port 5 port 5 is an 8-bit bi-directional general- purpose i/o port which can be alternatively used for asc0/1 or msc0/1 lines. p5.0 p5.1 p5.2 p5.3 p5.4 p5.5 p5.6 p5.7 b13 a13 a14 b14 c15 c14 b15 a15 i/o o i/o o o o i o o i rxd0a txd0a rxd1a txd1a en00 rready0b sdi0 en10 tvalid0b sdi1 asc0 receiver input / output a asc0 transmitter output a asc1 receiver input / output a asc1 transmitter output a p5.3 is latched with the rising edge of porst if bypass = 1 and stored in inverted state as bit osc_con.mosc. msc0 device select output 0 mli0 receive channel ready output b msc0 serial data input msc1 device select output 0 mli0 transmit channel valid output b msc1 serial data input table 2 pin definitions and functions (cont?d) symbol pins i/o pad class power supply functions www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 general device information data sheet 23 v1.0, 2008-04 p6 i/o a2 v ddp port 6 port 6 is a 12-bit bi-directional general- purpose i/o port which can be alternatively used for ssc1, asc0/1, and can i/o lines. p6.4 p6.5 p6.6 p6.7 p6.8 p6.9 p6.10 p6.11 p6.12 p6.13 p6.14 p6.15 f3 g4 e3 g3 f4 e4 f2 e2 e1 g2 f1 g1 o i i o i/o i i i/o o o i i/o o o i o i o mtsr1 mrst1 sclk1 slsi1 rxdcan0 rxd0b txdcan0 txd0b rxdcan1 rxd1b txdcan1 txd1b rxdcan2 txdcan2 rxdcan3 txdcan3 ssc1 master transmit output / ssc1 slave receive input ssc1 master receive input / ssc1 slave transmit output ssc1 clock input / output ssc1 slave select input can node 0 receiver input asc0 receiver input / output b can node 0 transmitter output asc0 transmitter output b can node 1 receiver input asc1 receiver input / output b can node 1 transmitter output asc1 transmitter output b can node 2 receiver input can node 2 transmitter output can node 3 receiver input can node 3 transmitter output table 2 pin definitions and functions (cont?d) symbol pins i/o pad class power supply functions www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 general device information data sheet 24 v1.0, 2008-04 p7 i/o a1 v ddp port 7 port 7 is an 8-bit bi-directional general- purpose i/o port which can be alternatively used as external trigger input lines and for adc0/1 external multiplexer control. p7.0 p7.1 p7.2 p7.3 p7.4 p7.5 p7.6 p7.7 r3 r2 u4 u3 t3 t2 t1 u2 i i o o o i i o o req4 req5 ad0emux2 ad0emux0 ad0emux2 req6 req7 ad1emux0 ad1emux1 external trigger input 4 external trigger input 5 adc0 external multiplexer control output 2 adc0 external multiplexer control output 0 adc0 external multiplexer control output 1 external trigger input 6 external trigger input 7 adc1 external multiplexer control output 0 adc1 external multiplexer control output 1 table 2 pin definitions and functions (cont?d) symbol pins i/o pad class power supply functions www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 general device information data sheet 25 v1.0, 2008-04 p8 i/o a1/a2 v ddp port 8 port 8 is an 8-bit bi-directional general- purpose i/o port which can be alternatively used for the mli1 interface or as gpta i/o lines. p8.0 p8.1 p8.2 p8.3 p8.4 p8.5 p8.6 p8.7 h2 h1 j3 j2 j1 k2 k3 k1 o i/o i i/o o i/o o i/o i i/o o i/o i i/o i i/o a2 a2 a1 a1 a2 a2 a2 a2 a1 a1 a2 a2 a1 a1 a1 a1 tclk1 in40/out40 tready1a in41/out41 tvalid1a in42/out42 tdata1 in43/out43 rclk1a in44/out44 rready1a in45/out45 rvalid1a in46/out46 rdata1a in47/out47 mli1 transmit channel clock output i/o line of gpta mli1 transmit channel ready input a i/o line of gpta mli1 transmit channel valid output a i/o line of gpta mli1 transmit channel data output i/o line of gpta mli1 receive channel clock input a i/o line of gpta mli1 receive channel ready output a i/o line of gpta mli1 receive channel validinput a i/o line of gpta mli1 receive channel data input a i/o line of gpta table 2 pin definitions and functions (cont?d) symbol pins i/o pad class power supply functions www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 general device information data sheet 26 v1.0, 2008-04 p9 i/o a2 v ddp port 9 port 9 is a 9-bit bi-directional general- purpose i/o port which can be alternatively used as gpta or msc0/1 i/o lines. p9.0 p9.1 p9.2 p9.3 p9.4 p9.5 p9.6 p9.7 p9.8 a19 b19 b20 a20 d18 d19 c19 d20 c20 i/o o i/o o i/o o i/o o i/o o i/o o i/o o i/o o o in48/out48 en12 in49/out49 en11 in50/out50 sop1b in51/out51 fclp1 in52/out52 en03 in53/out53 en02 in54/out54 en01 in55/out55 sop0b fclp0b i/o line of gpta msc1 device select output 2 i/o line of gpta msc1 device select output 1 i/o line of gpta msc1 serial data output i/o line of gpta msc1 clock output i/o line of gpta msc0 device select output 3 i/o line of gpta msc0 device select output 2 i/o line of gpta msc0 device select output 1 i/o line of gpta msc0 serial data output msc0 clock output table 2 pin definitions and functions (cont?d) symbol pins i/o pad class power supply functions www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 general device information data sheet 27 v1.0, 2008-04 p10 p10.0 p10.1 p10.2 p10.3 a21 b21 c21 d21 i i i i i a1 v ddp hardware configuration inputs / port 10 these inputs are boot mode (hardware configuration) control inputs. they are latched with the rising edge of hdrst . port 10 input line 0 / hwcfg0 port 10 input line 1 / hwcfg1 port 10 input line 2 / hwcfg2 port 10 input line 3 / hwcfg3 after reset ( hdrst = 1) the state of the port 10 input pins may be modified from the reset configuration state. there actual state can be read via software (p10_in register). during normal operation input hwcfg1 serves as emergency shut-off control input for certain i/o lines (e.g. gpta related outputs). dedicated peripheral i/os slso0 ae14 o a2 v ddp ssc0 slave select output line 0 slso1 ac15 o ssc0 slave select output line 1 mtsr0 af15 o i ssc0 master transmit output / ssc0 slave receive input mrst0 ae15 i o ssc0 master receive input / ssc0 slave transmit output sclk0 af14 i/o ssc0 clock input/output slsi0 ad15 i ssc0 slave select input table 2 pin definitions and functions (cont?d) symbol pins i/o pad class power supply functions www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 general device information data sheet 28 v1.0, 2008-04 msc outputs fclp0a fcln0 sop0a son0 fclp1a fcln1 sop1a son1 c18 c17 c16 d17 a17 b17 b16 a16 o o o o o o o o c v ddp lvds msc clock and data outputs 2) msc0 differential driver clock output positive a msc0 differential driver clock output negative msc0 differential driver serial data output positive a msc0 differential driver serial data output negative msc1 differential driver clock output positive a msc1 differential driver clock output negative msc1 differential driver serial data output positive a msc1 differential driver serial data output negative table 2 pin definitions and functions (cont?d) symbol pins i/o pad class power supply functions www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 general device information data sheet 29 v1.0, 2008-04 analog inputs an[43:0] an0 an1 an2 an3 an4 an5 an6 an7 an8 an9 an10 an11 an12 an13 an14 an15 an16 an17 an18 an19 an20 an21 an22 an23 an24 an25 an26 an27 an28 an29 an30 an31 ae1 ad2 aa4 ab3 ac2 aa3 ad1 ab4 ac1 ab2 y3 aa2 ab1 w3 y2 aa1 v4 w2 y1 v3 w1 v2 v1 u1 ac8 ad8 ac7 ad7 ae6 af6 ae7 af7 i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i d ? adc analog input port the adc analog input port provides 44 analog input lines for the a/d converters adc0, adc1, and fadc. analog input 0 analog input 1 analog input 2 analog input 3 analog input 4 analog input 5 analog input 6 analog input 7 analog input 8 analog input 9 analog input 10 analog input 11 analog input 12 analog input 13 analog input 14 analog input 15 analog input 16 analog input 17 analog input 18 analog input 19 analog input 20 analog input 21 analog input 22 analog input 23 analog input 24 analog input 25 analog input 26 analog input 27 analog input 28 analog input 29 analog input 30 analog input 31 table 2 pin definitions and functions (cont?d) symbol pins i/o pad class power supply functions www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 general device information data sheet 30 v1.0, 2008-04 an32 an33 an34 an35 an36 an37 an38 an39 an40 an41 an42 an43 ac3 ae2 ad3 ad5 ae3 af2 ac4 af3 ad4 ae4 ac5 af4 i i i i i i i i i i i i d ? adc analog input port (cont?d) analog input 32 analog input 33 analog input 34 analog input 35 analog input 36 analog input 37 analog input 38 analog input 39 analog input 40 analog input 41 analog input 42 analog input 43 tr[15:0] tr0 tr1 tr2 tr3 tr4 tr5 tr6 tr7 tr8 tr9 tr10 tr11 tr12 tr13 tr14 tr15 u12 t12 u11 t11 u10 r12 r10 r11 m11 m10 l11 l10 k10 k11 l12 k12 o o o o o o o o o o o o o o o o o a3 v ddp ocds level 2 debug trace lines 2) (located on center balls) trace output line 0 trace output line 1 trace output line 2 trace output line 3 trace output line 4 trace output line 5 trace output line 4 trace output line 7 trace output line 8 trace output line 9 trace output line 10 trace output line 11 trace output line 12 trace output line 13 trace output line 14 trace output line 15 trclk t10 o a4 trace clock for ocds level 2 debug trace lines 1) (located on a center ball) table 2 pin definitions and functions (cont?d) symbol pins i/o pad class power supply functions www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 general device information data sheet 31 v1.0, 2008-04 system i/o trs t f23 i a2 v ddp jtag module reset/enable input 2) tck e24 i a2 jtag module clock input 2) tdi e25 i a1 jtag module serial data input tdo d25 o a2 jtag module serial data output tms f24 i a1 jtag module state machine control input brki n c26 i/o a3 ocds break input (alternate output) 2) brk ou t d26 i/o a3 ocds break output (alternate input) 2) nm i a22 i ? non-maskable interrupt input (input pad with input spike-filter.) hdrs t a23 i/o a2 hardware reset input / reset indication output (open drain pad with input spike-filter.) pors t b22 i ? power-on reset input (input pad with input spike-filter.) bypass a24 i a1 pll bypass select input this input has to be held stable between to power-on resets. with bypass = 1 the spike filters in the hdrst , porst , and nmi inputs are switched off. test mod e b23 i ? test mode select input for normal operation of the TC1796, this pin should be connected to high level. (input pad, test function only, without input spike-filter.) tstres g24 i ? test reset input for normal operation of the TC1796, this pin should be connected to low level. otherwise an unpredictable reset behavior may occur. (input pad, test function only, without input spike-filter.) table 2 pin definitions and functions (cont?d) symbol pins i/o pad class power supply functions www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 general device information data sheet 32 v1.0, 2008-04 xtal1 xtal2 g26 g25 i o n.a. v dd oscillator / pll / clock generator input / output pins 2) n.c. a1 c22 g23 h3 af1 af26 ac21 ad23 ae22 ae23 ? ? ? not connected these pins are reserved for future extension and should not be connected externally. power supplies v ddm w4 ? ? ? adc0/1 analog part power supply (3.3v) v ssm y4 ? ? ? adc0/1 analog part ground for v ddm v ddmf ae9 ? ? ? fadc analog part power supply (3.3v) v ssmf af9 ? ? ? v fadc analog part ground for v ddaf v ddaf ac9 ? ? ? fadc analog part log. pow. sup. (1.5v) v ssaf ad9 ? ? ? fadc analog part log ground for v ddaf v aref0 ae5 ? ? ? adc0 reference voltage v agnd0 af5 ? ? ? adc0 reference ground v aref1 ad6 ? ? ? adc1 reference voltage v agnd1 ac6 ? ? ? adc1 reference ground v faref af8 ? ? ? fadc reference voltage v fagnd ae8 ? ? ? fadc reference ground v ddosc 3) f26 ? ? ? main oscillator power supply (1.5v) v ddosc3 e26 ? ? ? main oscillator power supply (3.3v) v ssosc 3) f25 ? ? ? main oscillator ground v ddfl3 a18 b18 ? ? ? power supply for flash (3.3v) v ddsbram r1 ? ? ? power supply for stand-by sram (1.5v) table 2 pin definitions and functions (cont?d) symbol pins i/o pad class power supply functions www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 general device information data sheet 33 v1.0, 2008-04 v ddebu h23 h24 h25 h26 m23 t23 y23 ac18 ac22 ? ? ? ebu power supply (2.3 - 3.3v) v dd b26 c25 d9 d16 d24 e23 h4 p23 r4 v23 ab23 ac11 ac20 ? ? ? core power supply (1.5v) v ddp a25 b24 c23 d7 d14 d22 k4 ac16 ad16 ae16 af16 ? ? ? port power supply (3.3v) (also for ocds) v ss see table 3 ? ? ? ground 15 v ss lines are located at outer balls. 47 v ss lines are located at center balls. 1) in order to minimize noise coupling to the on-chip a/d converters, it is recommended to use these pins as less as possible in strong driver mode. table 2 pin definitions and functions (cont?d) symbol pins i/o pad class power supply functions www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 general device information data sheet 34 v1.0, 2008-04 2) in case of a power-fail condition (one or more power supply voltages drop below the specified voltage range), an undefined output driving level may occur at these pins. 3) not bonded externally in the bc and bd steps of TC1796. an option for bonding them in future steps and products is kept open. table 3v ss balls v ss outer balls v ss center balls a26, b25, c24, d8, d15, d23, j4, l23, r23, t4, w23, ac10, ac17, ac19, ac23 k[17:13], l[17:13], m[17:12], n[17:10], p[17:10], r[17:13], t[17:13], u[17:13] www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 general device information data sheet 35 v1.0, 2008-04 2.5.1 pull-up/pull-down behavior of the pins table 4 list of pull-up/pull-down reset behavior of the pins pins porst = 0 porst = 1 tstres, tdi , tms, testmode , brkout , brkin , all gpios, rd , rd/ wr , adv , bc[3:0] , mr/ w, wait , baa , hold , hlda , breq , d[31:0], a[23,0], cs[3:0] , cscomb weak pull-up device active nmi , porst weak pull-down device active bypass, slso0, slso1, mtsr0, mrst0, sclk0, slsi0, tdo, bfclki weak pull-up device active high-impedance bfclko weak pull-up device active push-pull driver active hdrst open-drain device drives 0 (strong pull-down) weak pull-up device active open-drain device active trst , tck high-impedance weak pull-down device active www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 functional description data sheet 36 v1.0, 2008-04 3 functional description the following section gives an overview of the sub systems and the modules of the TC1796 and their connectivity. 3.1 system architecture and on-chip bus systems the TC1796 has four independent on-chip buses (see also TC1796 block diagram in figure 1 ): ? program local memory bus (plmb) ? data local memory bus (dlmb) ? system peripheral bus (spb) ? remote peripheral bus (rpb) the two lmb buses (program local memory bus plmb and data local memory bus dlmb) connect the tricore cpu to its local resources for data and instruction fetches. the plmb/dlmb buses are synchronous and pipelined buses with variable block size transfer support. the protocol supports 8-, 16-, 32-, and 64-bit single transactions and variable length 64-bit block transfers. the system peripheral bus (spb) is accessible by the cpu via the lfi bridge. the lfi bridge is a bi-directional bus bridge between the dlmb and the spb. it supports all transactions types of both buses, dlmb bus and fpi bus. it handles address translation and transaction type translation between the two buses. the lfi bridge further supports the pipelining of both connected buses. therefor e, no additional delay is created except for bus protocol conversions. the remote peripheral bus (rpb) connects the peripherals with high data rates (ssc, adc, fadc) with the dual-port memory (dpram) in the dmi, relieving the spb and the plmb/dlmb buses from these data transfers. the rpb is controlled by a bus switch which is located in the dma controller. the two lmb buses are running at cpu clock speed (clock rate of f cpu ) while spb and rpb are running at system clock speed (clock rate of f sys ). note that f sys can be equal to f cpu or half the f cpu frequency. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 functional description data sheet 37 v1.0, 2008-04 3.2 on-chip memories as shown in the TC1796 block diagram on page 10 , some of the TC1796 units provide on-chip memories that are used as program or data memory. ? program memory in pmu and pmi ?2 mbyte on-chip program flash (pflash) ?16 kbyte boot rom (brom) ?48 kbyte scratch-pad ram (spram) ?16 kbyte instruction cache (icache) ? data memory in dmu, pmu and dmi ?56 kbyte local data ram (ldram) ?8 kbyte dual-port ram (dpram) ?64 kbyte data memory (sram) ?16 kbyte data memory (sbram) for standby operation during power-down ? 128 kbyte on-chip data flash (dflash) ? memory of the pcp2 ?32 kbyte code memory (cmem) ?16 kbyte parameter memory (pram) ? on-chip srams with parity error detection features of the program flash ?2 mbyte on-chip program flash memory ? usable for instruction code exec ution or constant data storage ? 256-byte wide program interface ? 256 bytes are programmed into pflash page in one step/command ? 256-bit read interface ? transfer from pflash to cpu/pmi by four 64-bit single-cycle burst transfers ? dynamic correction of single-bit errors during read access ? detection of double bit errors ? fixed sector architecture ? eight 16 kbyte, one 128 kbyte, one 256 kbyte, and three 512 kbyte sectors ? each sector separately erasable ? each sector separately write-protectable ? configurable read protection for complete pflash with sophisticated read access supervision, combined with write protection for complete pflash (protection against ?trojan horse? software) ? configurable write protection for each sector ? each sector separately write-protectable ? with capability to be re-programmed ? with capability to be locked forever (otp) ? password mechanism for temporarily disable write or read protection ? on-chip programming voltage generation ? pflash is delivered in erased state (read all zeros) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 functional description data sheet 38 v1.0, 2008-04 ? jedec standard based command sequences for pflash control ? write state machine controls programming and erase operations ? status and error reporting by status flags and interrupt ? margin check for detection of problematic pflash bits features of the data flash ? 128 kbyte on-chip data flash memory, organized in two 64 kbyte banks ? usable for data storage with eeprom functionality ? 128 byte program interface ? 128 bytes are programmed into one dflash page by one step/command ? 64-bit read interface (no burst transfers) ? dynamic correction of single-bit errors during read access ? detection of double bit errors ? fixed sector architecture ?two 64 kbyte banks/sectors ? each sector separately erasable ? configurable read protection (combined with write protection) for complete dflash together with pflash read protection ? password mechanism to temporarily disable write and read protection ? erasing/programming of one bank possible while reading data from the other bank ? programming of one bank possible while erasing the other bank ? on-chip generation of programming voltage ? dflash is delivered in erased state (read all zeros) ? jedec-standard based command s equences for dflash control ? write state machine controls programming and erase operations ? status and error reporting by status flags and interrupt ? margin check for detection of problematic dflash bits www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 functional description data sheet 39 v1.0, 2008-04 3.3 architectural address map table 5 shows the overall architectural address map as defined for the tricore and implemented in TC1796. table 5 TC1796 architectural address map seg- ment contents size description 0-7 global 8 256 mbyte reserved (mmu space), cached 8 global memory 256 mbyte ebu (246 mbyte), pmu with pflash, dflash, brom, memory reserved for emulation, cached 9 global memory 256 mbyte fpi space; cached 10 global memory 256 mbyte ebu (246 mbyte), pmu with pflash, dflash, brom, memory reserved for emulation, non- cached 11 global memory 256 mbyte fpi space; non-cached 12 local lmb memory 256 mbyte dmu, bottom 4 mbyte visible from fpi bus in segment 14, cached 13 dmi 64 mbyte local data memory ram, non-cached pmi 64 mbyte local code memory ram, non-cached extper 96 mbyte external peripheral space, non-cached extemu 16 mbyte external emulator range, non-cached bootrom 16 mbyte boot rom space, brom mirror; non-cached 14 extper 128 mbyte external peripheral space non-speculative, no execution, non-cached cpu[0 ..15] image region 16 8 mbyte non-speculative, no execution, non-cached 15 lmbper csfrs intper 256 mbyte csfrs of cpus[0 ..15]; lmb & internal peripheral space; non-speculative, no execution, non-cached www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 functional description data sheet 40 v1.0, 2008-04 3.4 memory protection system the TC1796 memory protection system specifies the addressable range and read/write permissions of memory segments available to the currently executing task. the memory protection system controls the position and range of addressable segments in memory. it also controls the kinds of read and write operations allowed within addressable memory segments. any illegal memory access is detected by the memory protection hardware, which then invokes the appropriate trap service routine (tsr) to handle the error. thus, the memory prot ection system protects critical system functions against both software and hardware errors. the memory protection hardware can also generate signals to the debug unit to facilitate tracing illegal memory accesses. there are two memory protection register sets in the TC1796, numbered 0 and 1, which specify memory protection ranges and permissions for code and data. the psw.prs bit field determines which of these is the set currently in use by the cpu. because the TC1796 uses a harvard-styl e memory architecture, each memory protection register set is broken down into a data protection register set and a code protection register set. each data protection register set can specify up to four address ranges to receive particular protection modes. each code protection register set can specify up to two address ranges to receive particular protection modes. each of the data protection register sets and code protection register sets determines the range and protection modes fo r a separate memory area. each contains register pairs which determine the address range (the data segment protection registers and code segment protection registers) and one register (data protection mode register) which determines the memory access modes which apply to the specified range. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 functional description data sheet 41 v1.0, 2008-04 3.5 external bus unit the external bus unit (ebu) of the TC1796 is the units that controls the transactions between external memories or peripheral units with the internal memories and peripheral units. the ebu is a part of the pmu and communicates with cpu and pmi via the program local memory bus. this configuratio n allows to get fast access times especially when using external burst flash memory devices. figure 4 ebu block diagram the following features are supported by the ebu: ? 64-bit internal program local memory bus (plmb) interface ? 32-bit external demultiplexed bus interface ? asynchronous read/write accesses support intel-style and motorola-style interface signals ? synchronous burst flash memory read ? five programmable regions associated each to one chip select output ? flexibly programmable access parameters for each chip select region ? little-endian and big-endian support ? programmable wait state control ? scalable external bus frequency ? derived from plmb frequency ( f cpu ) divided by 1, 2, 3, or 4 ? max. 75 mhz mcb0571 3 a ddress b us c ontrol l ines progra m local memor y bus data path control external bus arbitration asynchronous access state machine burst access state machine plmb address region selection plmb data plmb interface slave master 32 external bus unit ebu address path control d ata b us a rbitration s ignals 24 64 64 32 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 functional description data sheet 42 v1.0, 2008-04 ? data buffering supported ? code prefetch buffer ? read/write buffer ? external bus arbitration control capability for the ebu bus ? automatic self-configuration on boot from external memory 3.6 peripheral control processor the peripheral control processor (pcp2) in the TC1796 performs tasks that would normally be performed by the combination of a dma controller and its supporting cpu interrupt service routines in a traditional computer system. it could easily be considered as the host processor?s first line of defence as an interrupt-handling engine. the pcp2 can off-load the cpu from having to service ti me-critical interrupts. this provides many benefits, including: ? avoiding large interrupt-driven task context-switching latencies in the host processor ? reducing the cost of interrupts in terms of processor register and memory overhead ? improving the responsiveness of interrupt service routines to data-capture and data- transfer operations ? easing the implementation of multitasking operating systems. the pcp2 has an architecture that efficiently supports dma-type transactions to and from arbitrary devices and memory addresses within the TC1796 and also has reasonable stand-alone computational capabilities. the pcp2 in the TC1796 contains an improved version of the tc1775?s pcp with the following enhancements: ? optimized context switching ? support for nested interrupts ? enhanced instruction set ? enhanced instruction execution speed ? enhanced interrupt queueing the pcp2 is made up of several modular blocks as follows (see figure 5 ): ? pcp2 processor core ? code memory (cmem) ? parameter memory (pram) ? pcp2 interrupt control unit (picu) ? pcp2 service request nodes (psrn) ? system bus interface to the flexible peripheral interface (fpi bus) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 functional description data sheet 43 v1.0, 2008-04 figure 5 pcp2 block diagram table 6 pcp2 instruction set overview instruction group description dma primitives efficient dma channel implementation load/store transfer data between pram or fpi memory and the general purpose registers, as well as move or exchange values between registers arithmetic add, subtract, compare and complement divide/multiply divide and multiply logical and, or, exclusive or, negate shift shift right or left, rotate right or left, prioritize bit manipulation set, clear, insert and test bits flow control jump conditionally, jump long, exit miscellaneous no operation, debug mcb05666a pcp2 processor core pcp2 service req. nodes psrns p cp 2 in te rru p t control unit picu parameter memory pram code memory cmem fp i-in terfa ce pcp2 interrupt arbitration bus cpu interrupt arbitration bus fpi bus www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 functional description data sheet 44 v1.0, 2008-04 3.7 dma controller and memory checker the direct memory access (dma) controller of the TC1796 transfers data from data source locations to data destination locations without intervention of the cpu or other on-chip devices. one data move operation is controlled by one dma channel. sixteen dma channels are provided in two independent dma sub-blocks with eight dma channels each. the bus switch provides the connection of two dma sub-blocks to the two fpi bus interfaces and an mli bus interface. in the TC1796, the fpi bus interfaces are connected to system peripheral bus and the remote peripheral bus. the third specific bus interface provi des a connection to micro link interface modules (two mli modules in the TC1796) and other dma-related devices (memory checker module in the TC1796). figure 6 shows the implementation details and interconnections of the dma module. figure 6 dma controller block diagram mcb05680 f dma sr[15:0] dma controller dma channels 00-07 dma sub-block 0 request selection/ arbitration dma sub-block 1 arbiter/ switch control bus switch fpi bus interface 0 dma channels 10-17 request selection/ arbitration fpi bus interface 1 mli interface dma interrupt control ch0n_out transaction control unit ch1n_out interrupt request nodes clock control address decoder transaction control unitl dma requests of on-chip periph. units memory checker mli0 mli1 system peripher al bus remote peripher al bus www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 functional description data sheet 45 v1.0, 2008-04 features ? 16 independent dma channels ? 8 dma channels in each dma sub-block ? up to 8 selectable request inputs per dma channel ? 2-level programmable priority of dma channels within a dma sub-block ? software and hardware dma request ? hardware requests by selected on-ch ip peripherals and external inputs ? programmable priority of the dma sub-blocks on the bus interfaces ? buffer capability for move actions on the bus es (at least 1 move per bus is buffered). ? individually programmable operation modes for each dma channel ? single mode: stops and disables dma channel after a predefined number of dma transfers ? continuous mode: dma channel remains enabled after a predefined number of dma transfers; dma transaction can be repeated. ? programmable address modification ? full 32-bit addressing capability of each dma channel ? 4 gbyte address range ? support of circular buffer addressing mode ? programmable data width of dma transfer/transaction: 8-bit, 16-bit, or 32-bit ? micro link bus interface support ? register set for each dma channel ? source and destination address register ? channel control and status register ? transfer count register ? flexible interrupt generation (the service request node logic for the mli channels is also implemented in the dma module) ? all buses connected to the dma module must work at the same frequency. ? read/write requests of the system bus side to the remote peripherals are bridged to the remote peripheral bus (only the dma is master on the rpb) memory checker the memory checker module (memchk) makes it possible to check the data consistency of memories. any spb bus mast er may access the memory checker. preferable the dma controller does it as described hereafter. it uses 8-bit, 16-bit, or 32- bit dma moves to read from the selected address area and to write the value read in a memory checker input register. with each write operation to the memory checker input register, a polynomial checksum calculation is triggered and the result of the calculation is stored in the memory checker result register. the memory checker uses the standard ethernet polynomial, which is given by: g 32 = x 32 + x 26 + x 23 + x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 + x +1 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 functional description data sheet 46 v1.0, 2008-04 note: although the polynomial above is used for generation, the generation algorithm differs from the one that is used by the ethernet protocol. 3.8 interrupt system the TC1796 interrupt system provides a flexible and time-efficient means for processing interrupts. an interrupt request can be servic ed either by the cpu or by the peripheral control processor (pcp). these units are called ?service providers?. interrupt requests are called ?service requests? rather than ?interrupt requests? in this document because they can be serviced by either of the service providers. each peripheral in the TC1796 can generate service requests. additionally, the bus control units, the debug unit, the pcp, and even the cpu itself can generate service requests to either of the two service providers. as shown in figure 7 , each TC1796 unit that can generate service requests is connected to one or more service request node s (srn). each srn contains a service request control register. two arbitration buses connect the srns with two interrupt control units, which handle interrupt arbitration among competing interrupt service requests, as follows: ? the interrupt control unit (icu) arbitrates service requests for the cpu and administers the cpu interrupt arbitration bus. ? the peripheral interrupt control unit (picu) arbitrates service requests for the pcp2 and administers the pcp2 interrupt arbitration bus. the pcp2 can make service requests directly to itself (via the picu), or it can make service requests to the cpu. the debug unit can generate service requests to the pcp2 or the cpu. the cpu can make service requests directly to itself (via the icu), or it can make service requests to the pcp. the cpu service request nodes are activated through software. depending on the selected system clock frequency f sys , the number of f sys clock cycles per arbitration cycle must be selected as follows: ? f sys < 60mhz: icr.conecyc = 1 and pcp_icr.conecyc = 1 ? f sys > 60mhz: icr.conecyc = 0 and pcp_icr.conecyc = 0 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 functional description data sheet 47 v1.0, 2008-04 figure 7 block diagram of the TC1796 interrupt system service req. nodes service req. nodes service requestors cpu interrupt control unit service req. nodes interrupt service providers pcp interrupt control unit mcb05742 4 srns 4 mli0 3 srns 3 ssc0 3 srns 3 ssc1 4 srns 4 asc0 4 srns 4 asc1 16 srns 16 multican 4 srns adc0 4 srns 4 adc1 4 srns 4 fadc 38 4 5 3 4 16 38 38 pcp interrupt arbitration bus cpu interrupt arbitration bus 5 srns 2 srns 2 pcp2 int. ack. ccpn 5 2 5 5 5 srns 5 int. req. pipn cpu ccpn int. ack. software & break- point interrupts icu 38 38 38 5 5 5 srns 5 2 srns 2 msc0 2 srns 2 msc1 2 2 srns 2 mli1 2 fpu 8 srns 1 srn 1 srn 1 srn 1 srn stm flash gpta0 gpta1 ltca2 service requestors dma dbcu pbcu rbcu sbcu 38 srns 38 srns 16 srns 2 srns 1 srn 1 srn 16 16 2 1 1 1 8 8 8 1 1 1 1 1 1 1 1 1 1 1 1 int. req. pipn picu 1 srn cerberus 1 1 1 ext. int. 2 srns 2 software 1 srn 1 1 1 4 16 2 2 1 1 1 2 2 4 4 4 4 4 16 4 4 4 3 3 3 2 4 2 2 2 4 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 functional description data sheet 48 v1.0, 2008-04 3.9 asynchronous/synchronous serial interfaces (asc0, asc1) figure 8 shows a global view of the functional blocks and interfaces of the two asynchronous/synchronous serial interfaces asc0 and asc1. figure 8 block diagram of the asc interfaces the asynchronous/synchronous serial interfaces provide serial communication between the TC1796 and other microcontrollers, microprocessors, or external peripherals. the asc supports full-duplex asynchronous communication and half-duplex synchronous communication. in synchronous mode, data is transmitted or received synchronous to a shift clock which is generated by the asc internally. in asynchronous mcb0577 3 asc0 module (kernel) port 5 & port 6 control asc1 module (kernel) p6.8 / rxd0 b p6.9 / txd0b interrupt control eir tbir tir rir clock control address decoder interrupt control f asc eir tbir tir rir p5.0 / rxd0 a p5.1 / txd0a p6.10 / rxd1 b p6.11 / txd1b p5.2 / rxd1 a p5.3 / txd1a rxd_i1 rxd_o rxd_i0 txd_o t o d ma asc0_rdr asc0_tdr t o d ma asc1_rdr asc1_tdr rxd_i1 rxd_o rxd_i0 txd_o a2 a2 a2 a2 a2 a2 a2 a2 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 functional description data sheet 49 v1.0, 2008-04 mode, 8-bit or 9-bit data transfer, parity generation, and the number of stop bits can be selected. parity, framing, and overrun error detection are provided to increase the reliability of data transfers. transmission and reception of data are double-buffered. for multiprocessor communication, a mechanism is included to distinguish address bytes from data bytes. testing is supported by a loop-back option. a 13-bit baud rate generator provides the asc with a separate serial clock signal which can be very accurately adjusted by a prescaler implemented as a fractional divider. each asc module, asc0 and asc1, communicates with the external world via two i/o lines. the rxd line is the receive data input signal (in synchronous mode also output). txd is the transmit output signal. in the tc 1796, the two i/o lines of each asc can be alternatively switched to different pairs of gpio lines. clock control, address decoding, and inte rrupt service request control are managed outside the asc module kernel. features ? full-duplex asynchronous operating modes ? 8-bit or 9-bit data frames, lsb first ? parity bit generation/checking ? one or two stop bits ? baud rate from 4.69 mbit/s to 1.12 bit/s (@ 75 mhz clock) ? multiprocessor mode for automatic address/data byte detection ? loop-back capability ? half-duplex 8-bit synchronous operating mode ? baud rate from 9.38 mbit/s to 763 bit/s (@ 75 mhz clock) ? double buffered transmitter/receiver ? interrupt generation ? on a transmit buffer empty condition ? on a transmit last bit of a frame condition ? on a receive buffer full condition ? on an error condition (frame, parity, overrun error) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 functional description data sheet 50 v1.0, 2008-04 3.10 high-speed synchronous serial interfaces (ssc0, ssc1) figure 9 shows a global view of the functional blocks and interfaces of the two high- speed synchronous serial interfaces ssc0 and ssc1. figure 9 block diagram of the ssc interfaces the ssc allows full-duplex and half-duplex serial synchronous communication up to 37.5 mbit/s (@ 75 mhz module clock) with receive and transmit fifo support. (fifo only in ssc0). the serial clock signal can be generated by the ssc itself (master mode) mca05791 clock control address decoder interrupt control f ssc0 address decoder interrupt control t o d ma f clc0 f ssc1 f clc1 clock control ssc0_rdr ssc0_tdr t o d ma ssc1_rdr ssc1_tdr port 2 control . . . mrstb mtsr master slsi1 slso[7:2] mrsta mtsrb mrst mtsra sclkb sclk sclka slave slave master slave master port 6 control mrstb mtsr master slso[7:2] mrsta mtsrb mrst mtsra sclkb sclk sclka slave slave master master mtsr 0 mrst 0 sclk 0 p6.5 / mrst 1 p6.4 / mtsr 1 p6.6 / sclk 1 slsi0 p2.2 / slso 2 p2.7 / slso 7 p6.7 / slsi1 slsi[7:2] 1) slsi1 slave slsi[7:2] 1) ssc enabled m/s selected slso 0 slso 1 1) these lines are not connected slso1 slso0 ssc0 module (kernel) 8-stage rxfifo 8-stage txfifo ssc1 module (kernel) eir tir rir eir tir rir a2 a2 a2 a2 a2 a2 a2 a2 a2 a2 a2 a2 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 functional description data sheet 51 v1.0, 2008-04 or can be received from an external master (slave mode). data width, shift direction, clock polarity and phase are programmable. this allows communication with spi- compatible devices. transmission and reception of data is double-buffered. a shift clock generator provides the ssc with a separate serial clock signal. one slave select input is available for slave mode operation. eight programmable slave select outputs (chip selects) are supported in master mode. the i/o lines of the ssc0 module are connected to dedicated device pins while the ssc1 module i/o lines are wired with general purpose i/o port lines. features ? master and slave mode operation ? full-duplex or half-duplex operation ? automatic pad control possible ? flexible data format ? programmable number of data bits: 2 to 16 bits ? programmable shift direction: lsb or msb shift first ? programmable clock polarity: idle low or high state for the shift clock ? programmable clock/data phase: data shift with leading or trailing edge of the shift clock ? baud rate generation from 37.5 mbit/s to 572.2 bit/s (@ 75 mhz module clock) ? interrupt generation ? on a transmitter empty condition ? on a receiver full condition ? on an error condition (receive, phase, baud rate, transmit error) ? flexible ssc pin configuration ? one slave select input slsi in slave mode ? eight programmable slave select outputs slso in master mode ? automatic slso generation with programmable timing ? programmable active level and enable control ? ssc0 with 8-stage receive fifo (rxfifo) and 8-stage transmit fifo (txfifo) ? independent control of rxfifo and txfifo ? 2- to 16-bit fifo data width ? programmable receive/transmit interrupt trigger level ? receive and transmit fifo filling level indication ? overrun error generation ? underflow error generation www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 functional description data sheet 52 v1.0, 2008-04 3.11 micro second bus interfaces (msc0, msc1) the micro second channel (msc) interfaces provides a serial communication link typically used to connect power switches or other peripheral devices. the serial communication link is build up by a fast synchronous downstream channel and a slow asynchronous upstream channel. figure 10 shows a global view the interface signals of the msc interface. figure 10 block diagram of the msc interfaces msc0 module (kernel) port 5 & port 9 control fcln clock control address decoder interrupt control downstream channel upstr. channel fclp en0 en1 en2 en3 son sop sdi[0] 1) sr[1:0] emgstopmsc altinl[15:0] 16 altinh[15:0] to dma p5.5 / sdi0 son0 sop0a p9.4 / en03 p9.5 / en02 p9.6 / en01 p5.4 / en00 fcln0 fclp0a p9.8 / fclp0 b p9.7 / sop0b sr[3:2] (from gpta) (from scu) msc1 module (kernel) mca0582 3 port 5 & port 9 control fcln clock control address decoder interrupt control f msc1 f clc1 downstream channel upstr. channel fclp en0 en1 en2 son sop sdi[0] 1) sr[1:0] altinl[15:0] altinh[15:0] to dma sr[3:2] (from gpta) p5.7 / sdi1 son1 sop1a p9.0 / en12 p9.1 / en11 p5.6 / en10 fcln1 fclp1a p9.3 / fclp1 b p9.2 / sop1b f msc0 f clc0 sr15 (from can) en3 n.c. 1) sdi[7:1] are connected to high level. 16 16 16 c a2 a2 a2 a2 a2 a2 a2 a2 a2 a2 a2 a2 a2 c c c c c c c www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 functional description data sheet 53 v1.0, 2008-04 the downstream and upstream channels of the msc module communicate with the external world via nine i/o li nes. eight output lines are required for the serial communication of the downstream channel (clock, data, and enable signals). one out of eight input lines sdi[7:0] is used as serial data input signal for the upstream channel. the source of the serial data to be transmitted by the downstream channel can be msc register contents or data that is provided at the altinl/altinh input lines. these input lines are typically connected to other on-chi p peripheral units (for example with a timer unit like the gpta). an emergency stop input signal allows to set bits of the serial data stream to dedicated values in emergency case. clock control, address decoding, and inte rrupt service request control are managed outside the msc module kernel. service request outputs are able to trigger an interrupt or a dma request. features ? fast synchronous serial interface to connect power switches in particular, or other peripheral devices via serial buses ? high-speed synchronous serial transmission on downstream channel ? maximum serial output clock frequency: f fcl = f msc /2 (= 37.5 mbit/s @ 75 mhz module clock) ? fractional clock divider for precise frequency control of serial clock f msc ? command, data, and passive frame types ? start of serial frame: software-controlled, timer-controlled, or free-running ? programmable upstream data frame length (16 or 12 bits) ? transmission with or without sel bit ? flexible chip select generation indicates status during serial frame transmission ? emergency stop without cpu intervention ? low-speed asynchronous serial reception on upstream channel ? baud rate: f msc divided by 8, 16, 32, 64, 128, 256, or 512 ? standard asynchronous serial frames ? parity error checker ? 8-to-1 input multiplexer for sdi lines ? built-in spike filter on sdi lines www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 functional description data sheet 54 v1.0, 2008-04 3.12 multican controller (can) figure 11 shows a global view of the multican module with its functional blocks and interfaces. figure 11 block diagram of multican module with time-triggered extension the multican module contains four independently operating can nodes with full-can functionality that are able to exchange data and remote frames via a gateway function. transmission and reception of can frames is handled in accordance with can specification v2.0 b (active). each can nod e can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. all four can nodes share a common set of message objects. each message object can be individually allocated to one of the can nodes. besides serving as a storage container for incoming and outgoing frames, message objects can be combined to build gateways between the can nodes or to setup a fifo buffer. the message objects are organized in double-chained linked lists, where each can node has it?s own list of message objects. a can node stores frames only into message multican module kernel mca0586 4 port 6 control can node 1 can control message object buffer 128 objects timing control and synchronization scheduler scheduletiming datamemory time-triggered extension ttcan can node 0 can node 2 txdc3 rxdc3 linked list control p6.13 / txdcan 2 p6.12 / rxdcan 2 p6.11 / txdcan 1 p6.10 / rxdcan 1 p6.9 / txdcan 0 p6.8 / rxdcan 0 can node 3 txdc2 rxdc2 txdc1 rxdc1 txdc0 rxdc0 p6.15 / txdcan 3 p6.14 / rxdcan 3 interrupt control f can f clc clock control address decoder ectt3 gpta0 int_ o15 dma int_o [3:0] int_o [15:4] p1.3 / req3 p7.5 / req7 ectt1 ectt2 scu ext.req. unit gpta1 ltca2 ectt4 ectt5 a2 a2 a2 a2 a2 a2 a2 a2 a1 a1 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 functional description data sheet 55 v1.0, 2008-04 objects that are allocated to the message object list of the can node, and it transmits only messages belonging to this message object list. a powerful, command-driven list controller performs all message object list operations. multican features ? can functionality conforms to can specification v2.0 b active for each can node (compliant to iso 11898) ? four independent can nodes ? 128 independent message objects (shared by the can nodes) ? dedicated control registers for each can node ? data transfer rate up to 1mbit/s, individually programmable for each node ? flexible and powerful message transfer control and error handling capabilities ? full-can functionality: message objects can be individually ? assigned to one of the four can nodes ? configured as transmit or receive object ? configured as message buffer with fifo algorithm ? configured to handle frames with 11-bit or 29-bit identifiers ? provided with programmable acceptance mask register for filtering ? monitored via a frame counter ? configured for remote monitoring mode ? automatic gateway mode support ? 16 individually programmable interrupt nodes ? analyzer mode for can bus monitoring www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 functional description data sheet 56 v1.0, 2008-04 time-triggered extension (ttcan) in addition to the event-driven can functionality, a deterministic behavior can be achieved for can node 0 by an extension module that supports time-triggered can (ttcan) functionality. the ttcan protoc ol is compliant with the confirmed standardization proposal for iso 11898-4 and fully conforms to the existing can protocol. the time-triggered functionality is added as highe r-layer extension (session layer) to the can protocol in order to be able to operate in safety critical applications. the new features allow a deterministic behavior of a can network and the synchronization of networks. a global time information is available. the time-triggered extension is based on a scheduler mechanism with a timing control unit and a dedicated timing data part. ttcan features ? full support of basic cycle and system matrix functionality ? support of reference messages level 1 and level 2 ? usable as time master ? arbitration windows supported in time-triggered mode ? global time information available ? can node 0 can be configured either for event-driven or for time-triggered mode ? built-in scheduler mechanism and a timing synchronization unit ? write protection for scheduler timing data memory ? module-external can time trigger inputs (ecttx lines) can be used as transmit trigger for a reference message ? timing-related interrupt functionality ? parity protection for scheduler memory www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 functional description data sheet 57 v1.0, 2008-04 3.13 micro link serial bus interface (mli0, mli1) the micro link interface (mli) is a fast syn chronous serial interface that allows to exchange data between microcontrollers of the 32-bit audo microcontroller family without intervention of a cpu or other bus masters. figure 12 shows how two microcontrollers are typically connected t ogether via their mli interfaces. the mli operates in both microcontrollers as a bus master on the system bus. figure 12 typical micro link interface connection features ? synchronous serial communication between mli transmitters and mli receivers located on the same or on different microcontroller devices ? automatic data transfer/request transactions between local/remote controller ? fully transparent read/write access supported (= remote programming) ? complete address range of remote controller available ? specific frame protocol to transfer commands, addresses and data ? error control by parity bit ? 32-bit, 16-bit, and 8-bit data transfers ? programmable baud rate: ? mli transmitter baud rate: max. f mli /2 (= 37.5 mbit/s @ 75 mhz module clock) ? mli receiver baud rate: max. f mli ? multiple remote (slave) controllers supported mli transmitter and mli receiver communicate with other off-chip mli receivers and mli transmitters via a 4-line se rial i/o bus each. several i/o lines of these i/o buses are available outside the mli module kernel as four-line output or input buses. figure 13 shows the functional blocks of the two mli modules with its interfaces. mca05869 controller 1 cpu peripheral b peripheral a mli system bus controller 2 cpu peripheral d peripheral c mli system bus memory memory www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 functional description data sheet 58 v1.0, 2008-04 figure 13 block diagram of the mli modules sr[3:0] f mli0 address decoder interrupt control clock control to dma sr[7:4] port 1 control p1.5 / tready0 a port 5 control treadya tclk treadyd tvalida tvalidd tdata transmitter receiver rclka rclkd rreadya rreadyd rvalida rvalidd rdataa rdatab treadyb rreadyb rvalidb rdatad tvalidb rclkb mli0 module (kernel) mca0590 6 p1.4 / tclk0 p1.3 / tready0 b p1.6 / tvalid0a p1.7 / tdata0 p1.8 / rclk0a p1.9 / rready0 a p1.10 / rvalid0 a p1.11 / rdata0 a p1.13 / rclk0b p1.14 / rvalid0 b p1.15 / rdata0 b p5.4 / rready0 b p5.6 / tvalid0b f dma brkout cerberus a1 a2 a2 a2 a1 a1 a2 a1 a1 a1 a1 a1 a2 a2 interrupt control mca0590 7 port 8 control sr[1:0] f mli1 address decoder clock control not connected treadya mli1 module (kernel) tclk sr[3:2] treadyd tvalida tvalidd tdata transmitter receiver rclka rclkd rreadya rreadyd rvalida rvalidd rdataa rdatad to dma sr[7:4] brkout p8.0 / tclk1 p8.1 / tready1 a p8.2 / tvalid1a p8.3 / tdata1 p8.4 / rclk1a p8.5 / rready1 a p8.6 / rvalid1a p8.7 / rdata1a f dma cerberus a2 a2 a2 a1 a1 a1 a2 a1 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 functional description data sheet 59 v1.0, 2008-04 3.14 general purpose timer array the gpta provides a set of timer, compare and capture functionalities that can be flexibly combined to form signal measurement and signal generation units. they are optimized for tasks typical of engine, gearbox, and electrical motor control applications, but can also be used to generate simple and complex signal waveforms needed in other industrial applications. the TC1796 contains two general purpose timer arrays (gpta0 and gpta1) with identical functionality, plus an additional local timer cell array (ltca2). figure 14 shows a global view of the gpta modules. figure 14 block diagram of the gpta modules signal generation unit mcb0591 0 gt1 gt0 fpc5 fpc4 fpc3 fpc2 fpc1 fpc0 pdl1 pdl0 dcm2 dcm1 dcm0 digital pll dcm3 gtc02 gtc01 gtc00 gtc31 global timer cell array gtc03 gtc30 clock bus gpta0 clock generation unit signal generation unit gt1 gt0 fpc5 fpc4 fpc3 fpc2 fpc1 fpc0 pdl1 pdl0 dcm2 dcm1 dcm0 digital pll dcm3 gtc02 gtc01 gtc00 gtc31 global timer cell array gtc03 gtc30 clock bus gpta1 clock generation unit clock conn. clock distribution unit f gpta f gpta ltc02 ltc01 ltc00 ltc63 local timer cell array ltc03 ltc62 ltc02 ltc01 ltc00 ltc63 local timer cell array ltc03 ltc62 ltc02 ltc01 ltc00 ltc63 local timer cell array ltc03 ltc62 ltca2 i/o line sharing unit i/o line sharing unit i/o line sharing unit interrupt sharing unit interrupt sharing unit interrupt sharing unit clock distribution unit www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 functional description data sheet 60 v1.0, 2008-04 3.14.1 functionality of gpta0/gpta1 each of the general purpose timer arrays (gpta0 and gpta1) provides a set of hardware modules required for high speed digital signal processing: ? filter and prescaler cells (fpc) support input noise filtering and prescaler operation. ? phase discrimination logic units (pdl) decode the direction information output by a rotation tracking system. ? duty cycle measurement cells (dcm) provide pulse-width measurement capabilities. ? a digital phase locked loop unit (pll) generates a programmable number of gpta module clock ticks during an input signal?s period. ? global timer units (gt) driven by various clock sources are implemented to operate as a time base for the associated global timer cells. ? global timer cells (gtc) can be programmed to capture the contents of a global timer on an external or internal event. a gtc may be also used to control an external port pin depending on the result of an internal compare operation. gtcs can be logically concatenated to provide a common external port pin with a complex signal waveform. ? local timer cells (ltc) operating in timer, capture, or compare mode may be also logically tied together to drive a common external port pin with a complex signal waveform. ltcs ? enabled in timer mode or capture mode ? can be clocked or triggered by various external or internal events. input lines can be shared by an ltc and a gt c to trigger their programmed operation simultaneously. the following sections summarize the specific features of the gpta units. the clock signal f gpta is the input clock of the gpta modules (max. 75 mhz in TC1796). clock generation unit ? filter and prescaler cell (fpc) ? six independent units ? three basic operating modes: prescaler, delayed debounce filter, immediate debounce filter ? selectable input sources: port lines, gpta module clock, fpc output of preceding fpc cell ? selectable input clocks: gpta module clock, prescaled gpta module clock, dcm clock, compensated or uncompensated pll clock. ? f gpta /2 maximum input signal frequency in filter modes ? phase discriminator logic (pdl) ? two independent units ? two operating modes (2 and 3 sensor signals) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 functional description data sheet 61 v1.0, 2008-04 ? f gpta /4 maximum input signal frequency in 2-sensor mode, f gpta /6 maximum input signal frequency in 3-sensor mode. ? duty cycle measurement (dcm) ? four independent units ? 0 - 100% margin and time-out handling ? f gpta maximum resolution ? f gpta /2 maximum input signal frequency ? digital phase locked loop (pll) ? one unit ? arbitrary multiplication factor between 1 and 65535 ? f gpta maximum resolution ? f gpta /2 maximum input signal frequency ? clock distribution unit (cdu) ? one unit ? provides nine clock output signals: f gpta , divided f gpta clocks, fpc1/fpc4 outputs, dcm clock, ltc prescaler clock signal generation unit ? global timers (gt) ? two independent units ? two operating modes (free running timer and reload timer) ? 24-bit data width ? f gpta maximum resolution ? f gpta /2 maximum input signal frequency ? global timer cell (gtc) ? 32 units related to the global timers ? two operating modes (capture, compare and capture after compare) ? 24-bit data width ? f gpta maximum resolution ? f gpta /2 maximum input signal frequency ? local timer cell (ltc) ? 64 independent units ? three basic operating modes (timer, capture and compare) for 63 units ? special compare modes for one unit ? 16-bit data width ? f gpta maximum resolution ? f gpta /2 maximum input signal frequency interrupt sharing unit ? 286 interrupt sources, generating up to 92 service requests www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 functional description data sheet 62 v1.0, 2008-04 i/o sharing unit ? interconnecting inputs and out puts from internal clocks, fpc, gtc, ltc, ports, and msc interface. 3.14.2 functionality of ltca2 one local timer cells area provides a set of local timer cells. ? 64 local timer cells (ltcs) ? three basic operating modes (timer, capture and compare) for 63 units. ? special compare modes for one unit ? 16-bit data width ? f gpta maximum resolution ? f gpta /2 maximum input signal frequency www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 functional description data sheet 63 v1.0, 2008-04 3.15 analog-to-digital converter (adc0, adc1) the two adc modules of the TC1796 are analog to digital converters with 8-bit, 10-bit, or 12-bit resolution including sample & hold functionality. figure 15 block diagram of the adc module interrupt control interrupt control clock control address decoder adc0 module kernel f adc sr [3:0] t o dma ain16 analog multiplexer mca06033 synchronization bridge v agnd0 v dd v ss v ddm v aref0 v ssm group 1 p7.2 / ad0emux0 p7.3 / ad0emux1 adc1 module kernel analog multiplexer address decoder ain16 analog input sharing crossbar an0 an1 an2 an41 an42 an43 die temp. sensor ain30 ain31 p7.6 / ad1emux0 p7.7 / ad1emux1 v agnd1 v dd v ss v ddm v aref1 v ssm not used f clc port 7 control port 7 control ain0 ain15 group 0 ain0 ain15 group 0 asgt sw0tr, sw0gt etr, egt qtr, qgt ttr, tgt external request unit (scu) ain31 asgt sw0tr, sw0gt etr, egt qtr, qgt ttr, tgt external request unit (scu) from gpta from ports from msc0 /1 from gpta from ports from msc0 /1 8 sr[7:4] sr[3:0] to dma p7.1 / ad0emux2 emux0 emux1 grps emux0 emux1 sr[7:4] 2 9 8 2 9 a1 a1 a1 d d d d d d a1 a1 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 functional description data sheet 64 v1.0, 2008-04 the a/d converters operate by the method of the successive approximation. a multiplexer selects between up to 32 analog inputs that can be connected with the 16 conversion channels in each adc module. an automatic self-calibration adjusts the adc modules to changing temperatures or process variations. external clock control, address decoding, and service request (interrupt) control is managed outside the adc module kernel. a synchronization bridge is used for synchronization of two adc modules. external trigger conditions are controlled by an external request unit. this unit generates the control signals for auto-scan control (asgt), software trigger control (sw0tr, sw0gt), the event trigger control (etr, egt), queue control (qtr, qgt), and timer trigger control (ttr, tgt). features ? 8-bit, 10-bit, 12-bit a/d conversion ? minimum conversion times (without sample time, @ 75 mhz module clock): ?1.05 s @ 8-bit resolution ?1.25 s @ 10-bit resolution ?1.45 s @ 12-bit resolution ? extended channel status information on request source ? successive approximation conversion method ? total unadjusted error (tue) of 2 lsb @ 10-bit resolution ? integrated sample & hold functionality ? direct control of up to 16(32) analog input channels per adc ? dedicated control and status registers for each analog channel ? powerful conversion request sources ? selectable reference voltages for each channel ? programmable sample and conversion timing schemes ? limit checking ? flexible adc module service request control unit ? synchronization of the two on-chip a/d converters ? automatic control of external analog multiplexers ? equidistant samples initiated by timer ? external trigger and gating inputs for conversion requests ? power reduction and clock control feature ? on-chip die temperature sensor output voltage measurement via adc1 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 functional description data sheet 65 v1.0, 2008-04 3.16 fast analog-to-digital converter unit (fadc) the fadc module of the TC1796 basically is a 4-channel a/d converter with 10-bit resolution that operates by the method of the successive approximation. the main fadc functional blocks shown in figure 16 are: ? the input stage contains the differential inputs and the programmable amplifier. ? the a/d converter is responsible for the analog-to-digital conversion. ? the data reduction unit contains programmable anti aliasing and data reduction filters. ? the channel trigger control block defines the trigger and gating conditions for the four fadc channels. the gating source inputs gs[7:0] and trigger source inputs ts[7:0] are connected with gpta0 module outputs, with gpio port lines, and external request unit outputs. ? the channel timers can independently trigger the conversion of each fadc channel. ? the a/d control block is responsible for the overall fadc functionality. the fadc module is supplied by the following power supply and reference voltage lines: ? v ddmf / v ddmf : fadc analog part power supply (3.3v) ? v ddaf / v ddaf : fadc analog part logic power supply (1.5v) ? v faref / v fagnd : fadc reference voltage/fadc reference ground www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 functional description data sheet 66 v1.0, 2008-04 figure 16 block diagram of the fadc module features ? extreme fast conversion: 21 cycles of f fadc (= 280ns @ f fadc = 75 mhz) ? 10-bit a/d conversion ? higher resolution by averaging of consecutive conversions is supported ? successive approximation conversion method ? four differential input channels ? offset and gain calibration support for each channel ? differential input amplifier with programmable gain of 1, 2, 4 and 8 for each channel ? free-running (channel timers) or triggered conversion modes ? trigger and gating control for external signals ? built-in channel timers for internal triggering ? channel timer request periods independently selectable for each channel ? selectable, programmable anti aliasing and data reduction filter block clock control address decoder mca0605 3 v fagnd v ddaf v ssaf v ddmf v faref v ssmf interrupt control ts[7:0] gs[7:0] f fadc f clc sr[3:0] fadc module kernel fain0p fain0n fain1p fain1n fain2p fain2n fain3p fain3n to dma external request unit (scu) gpta0 out1 out9 out18 out26 out2 out10 out19 out27 pdout2 pdout3 an24 an25 an26 an27 an28 an29 an30 an31 p1.0 / req 0 p1.1 / req 1 p7.0 / req 4 p7.1 / req 5 d d d d d d d d a1 a1 a1 a1 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 functional description data sheet 67 v1.0, 2008-04 3.17 system timer the TC1796?s stm is designed for global system timing applications requiring both high precision and long range. features ? free-running 56-bit counter ? all 56 bits can be read synchronously ? different 32-bit portions of the 56-bit counter can be read synchronously ? flexible interrupt generation based on compare match with partial stm content ? driven by max. 75 mhz (= f sys , default after reset = f sys /2) ? counting starts automatically after a reset operation ? stm is reset by: ? watchdog reset ? software reset (rst_req.rrstm must be set) ? power-on reset ? stm is not reset at a hardware reset ? stm can be halted in debug/suspend mode the stm is an upward counter, running either at the system clock frequency f sys or at a fraction of it. in case of a power-on reset, a watchdog reset, or a software reset, the stm is reset. after one of these reset conditions , the stm is enabled and immediately starts counting up. it is not possible to affect the contents of the timer during normal operation of the TC1796. the timer registers can only be read but not written to. the stm can be optionally disabled or suspended for power-saving and debugging purposes via its clock control register. in suspend mode of the TC1796, the stm clock is stopped but all registers are still readable. the system timer can be read in sections from seven registers, stm_tim0 through stm_tim6, which select increasingly higher-order 32-bit ranges of the system timer. these can be viewed as individual 32-bit timers, each with a different resolution and timing range. for getting a synchronous and consistent reading of the complete stm contents, a capture register (stm_cap), is im plemented. it latches the contents of the high part of the stm each time when one of the registers stm_tim0 to stm_tim5 is read. thus, it holds the upper value of the timer at exactly the same time when the lower part is read. the second read operation would then read the contents of the stm_cap to get the complete timer value. the content of the 56-bit system timer can be compared against the content of two compare values stored in the compare registers. interrupts can be generated on a compare match of the stm with the stm_cmp0 or stm_cmp1 registers. the maximum clock period is 2 56 f stm . at f stm = 75 mhz, for example, the stm counts 30.47 years before overflowing. thus, it is capable of continuously timing the entire expected product life-time of a system without overflowing. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 functional description data sheet 68 v1.0, 2008-04 figure 17 shows an overview on the system timer with the options for reading parts of stm contents. figure 17 general block diagram of the stm module registers stm module 00 h stm_cap stm_tim6 stm_tim5 00 h 55 47 39 31 23 15 7 56-bit system timer address decoder clock control enable / disable f stm mcb0574 6 31 23 15 7 compare register 0 interrupt control compare register1 stmir1 stmir0 porst 0 0 31 23 15 7 0 stm_tim4 stm_tim3 stm_tim2 stm_tim1 stm_tim0 stm_cmp1 stm_cmp0 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 functional description data sheet 69 v1.0, 2008-04 3.18 watchdog timer the watchdog timer (wdt) provides a highly reliable and secure way to detect and recover from software or hardware failur e. the wdt helps to abort an accidental malfunction of the TC1796 in a user-specifie d time period. when enabled, the wdt will cause the TC1796 system to be reset if the wdt is not serviced within a user- programmable time period. the cpu must service the wdt within this time interval to prevent the wdt from causing a TC1796 system reset. hence, routine service of the wdt confirms that the system is functioning properly. in addition to this standard ?watchdog? function, the wdt incorporates the endinit feature and monitors its modifications. a system-wide line is connected to the end-of- initialization (endinit) feature and monitors its modifications. a system-wide line is connected to the wdt_con0.endinit bit, serv ing as an additional write-protection for critical registers (besides supervisor mode protection) a further enhancement in the TC1796?s wdt is its reset pre-warning operation. instead of immediately resetting the device on the detection of an error (the way that standard watchdogs do), the wdt first issues an non-maskable interrupt (nmi) to the cpu before finally resetting the device at a specified time period later. this gives the cpu a chance to save system state to memory for later examination of the cause of the malfunction, an important aid in debugging. features ? 16-bit watchdog counter ? selectable input frequency: f sys /256 or f sys /16384 ? 16-bit user-definable reload value for normal watchdog operation, fixed reload value for time-out and pre-warning modes ? incorporation of the endinit bit and monitoring of its modifications ? sophisticated password access mechanism with fixed and user-definable password fields ? proper access always requires two writ e accesses. the time between the two accesses is monitored by the wdt and limited. ? access error detection: invalid password (during first access) or invalid guard bits (during second access) trigger the watchdog reset generation. ? overflow error detection: an overflow of the counter triggers the watchdog reset generation. ? watchdog function can be disabled; access protection and endinit monitor function remain enabled. ? double reset detection: if a watchdog induced reset occurs twice, a severe system malfunction is assumed and the TC1796 is held in reset until a power-on reset. this prevents the device from being periodically reset if, for instance, connection to the external memory has been lost such that even system initialization could not be performed www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 functional description data sheet 70 v1.0, 2008-04 ? important debugging support is provided through the reset pre-warning operation by first issuing an nmi to the cpu before finally resetting the device after a certain period of time. 3.19 system control unit the system control unit (scu) of the TC1796 handles several system control tasks. these system control tasks of the scu are: ? clock system selection and control ? reset and boot operation control ? power management control ? configuration input sampling ? external request unit ? system clock output control ? chip select generation for ebu ? ebu pull devices control ? on-chip sram parity control ? pad driver temperature compensation control ? emergency stop input control for gpta outputs ? die temperature sensor ? gpta1 input in0 control ? pad test mode control for dedicated pins ? odcs level 2 trace control ? nmi control ? miscellaneous scu control 3.20 boot options the TC1796 booting schemes provide a number of different boot options for the start of code execution. table 7 shows the boot options available in the TC1796. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 functional description data sheet 71 v1.0, 2008-04 table 7 TC1796 boot selections brkin hwcfg [3:0] type of boot boot rom exit jump address normal boot options 1 0000 b enter bootstrap loader mode 1: serial asc0 boot via asc0 pins d400 0000 h 0001 b enter bootstrap loader mode 2: serial can boot via can pins 0010 b start from internal pflash a000 0000 h 0011 b alternate boot mode (abm): start from internal pflash after crc check is correctly executed; enter a serial bootstrap loader mode 1) if crc check fails. as defined in abm header or d400 0000h 0100 b start from external memory with ebu as master, using cs0 ; automatic ebu configuration 2) ; a100 0000 h 0101 b alternate boot mode (abm): start from external memory with crc check and ebu as master, using cs0 ; enter a serial bootstrap loader mode 2) if crc checks fails; automatic ebu configuration 2) ; as defined in abm header or d400 0000h 0110 b start from external memory with ebu as participant, using cs0 ; automatic ebu configuration 2) ; a100 0000 h 0111 b alternate boot mode (abm): start from external memory with crc check and ebu as participant, using cs0 ; enter a serial bootstrap loader mode 2) if crc checks fails; automatic ebu configuration 2) ; as defined in abm header or d400 0000h 1000 b start from emulation memory if emulation device TC1796ed is available; in case of TC1796: execute stop loop; if TC1796ed: aff0 0000h 1111 b enter bootstrap loader mode 3: serial asc0 boot via can pins d400 0000 h others reserved; execute stop loop; ? www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 functional description data sheet 72 v1.0, 2008-04 debug boot options 0 0000 b tri-state chip ? 1000 b go to external emulator space with ebu as master, using csemu / cscomb de00 0000 h others reserved; execute stop loop; ? 1) the type of the alternate bootstrap loader mode is selected by the value of the scu_sclir.swopt[2:0] bit field, which contains the levels of the p0.[2:0] latched in with the rising edge of the hdrst . for more details on abm, see the user?s manual. 2) the ebu fetches the boot configuration from address offset 4 using cs0. table 7 TC1796 boot selections (cont?d) brkin hwcfg [3:0] type of boot boot rom exit jump address www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 functional description data sheet 73 v1.0, 2008-04 3.21 power management system the TC1796 power management system allows software to configure the various processing units so that they automatically adjust to draw the minimum necessary power for the application. there are three power management modes: ?run mode ? idle mode ? sleep mode the operation of each system component in ea ch of these states can be configured by software. the power-management modes provide flexible reduction of power consumption through a combination of techniques, including stopping the cpu clock, stopping the clocks of other system component s individually, and individually clock- speed reduction of some peripheral components. besides these explicit software-controlled power-saving modes, in the TC1796 special attention has been paid for automatic power-saving in those operating units which are currently not required or idle. in that case they are shut off automatically until their operation is required again. table 8 describes the features of the power management modes. in typical operation, idle mode and sleep mode may be entered and exited frequently during the run time of an application. for example, system software will typically cause the cpu to enter idle mode each time it has to wait for an interrupt before continuing its tasks. in sleep mode and idle mode, wake-up is performed automatically when any enabled interrupt signal is detected, or if the watchdog timer signals the cpu with an nmi trap. table 8 power management mode summary mode description run the system is fully operational. all clocks and peripherals are enabled, as determined by software. idle the cpu clock is disabled, waiting for a condition to return it to run mode. idle mode can be entered by software when the processor has no active tasks to perform. all peripherals remain powered and clocked. processor memory is accessible to peripherals. a reset, watchdog timer event, a falling edge on the nmi pin, or any enabled interrupt event will return the system to run mode. sleep the system clock signal is distributed only to those peripherals programmed to operate in sleep mode. the other peripheral module will be shut down by the suspend signal. interrupts from operating peripherals, the watchdog timer, a falling edge on the nmi pin, or a reset event will return the system to run mode. entering this state requires an orderly shut-down controlled by the power management state machine. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 functional description data sheet 74 v1.0, 2008-04 3.22 on-chip debug support figure 18 shows a block diagram of the TC1796 ocds system. figure 18 ocds system block diagram the TC1796 basically supports three levels of debug operation: ? ocds level 1 debug support ? ocds level 2 debug support ? ocds level 3 debug support sbcu m u x mcb05756_mod tck tms tdi tdo remote peripheral bus multi core break switch (mcbs) jtag debug interface (jdi) ocds system control unit (oscu) trst brkin brkout tr[15:0] trclk jtag controller cerberus spb peripheral unit 1 rpb peripheral unit 1 rpb peripheral unit n dma controller ( bus bridge) rbcu system peripheral bus watchdog timer (wdt ) pcp2 spb peripheral unit m break & suspend si gnals enable, control, r eset signals tricore cpu www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 functional description data sheet 75 v1.0, 2008-04 ocds level 1 debug support the ocds level 1 debug support is mainly assigned for real-time software debugging purposes which have a demand for low-cost standard debugger hardware. the ocds level 1 debug support is based on a jtag interface which can be used by the external debug hardware to communicate with the system. the on-chip cerberus module controls the interactions between th e jtag interface and the on-chip modules. the external debug hardware may become master of the internal buses and read or write the on-chip register/memory resources. the cerberus also allows to define breakpoint and trigger conditions as well as to control user program execution (run/stop, break, single-step). ocds level 2 debug support the ocds level 2 debug support allows to implement program tracing capabilities for enhanced debuggers by extending the ocds level 1 debug functionality with an additional 16-bit wide trace port with trace clock. with the trace extension the following four trace capabilities are provided (only o ne of the four trace capabilities can be selected at a time): ? trace capability of the cpu program flow ? trace capability of the pcp2 program flow ? trace capability of the dma controller transaction requests ? trace capability of the dma controller move engine status information ocds level 3 debug support the ocds level 3 debug support is based on a special emulation device, the TC1796ed, which provides additional features required for high-end emulation purposes. the TC1796ed is a device which includes the TC1796 product chip and additional emulation extension hardware in a package with the same footprint as the TC1796. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 functional description data sheet 76 v1.0, 2008-04 3.23 clock generation and pll the TC1796 clock system performs the following functions: ? acquires and buffers incoming clock signals to create a master clock frequency ? distributes in-phase synchronized clock signals throughout the TC1796?s entire clock tree ? divides a system master clock frequency into lower frequencies required by the different modules for operation. ? dynamically reduces power consumptio n during operation of functional units ? statically reduces power consumption through programmable power-saving modes ? reduces electromagnetic interference (emi) by switching off unused modules the clock system must be operat ional before the TC1796 is able to run. therefore, it also contains special logic to handle power-up and reset operations. its services are fundamental to the operation of the entire system, so it contains special fail-safe logic. features ? pll operation for multiplying clock source by different factors ? direct drive capability for direct clocking ? comfortable state machine for secure switching between basic pll, direct or prescaler operation ? sleep and power-down mode support the TC1796 clock generation unit (cgu) as shown in figure 19 allows a very flexible clock generation. it basically consists of an main oscillator circuit and a phase- locked loop (pll). the pll can converts a low-fr equency external clock signal from the oscillator circuit to a high-speed internal clock for maximum performance. the system clock f sys is generated from an oscillator clock f osc in either of four hardware/software selectable ways: ? direct drive mode (pll bypass): in direct drive mode, the pll is bypassed and the cgu clock outputs are directly fed from the clock signal f osc , i.e. f cpu = f osc and f sys = f osc /2 or f osc . this allows operation of the TC1796 with a reasonably small fundamental mode crystal. ? vco bypass mode (prescaler mode): in vco bypass mode, f cpu and f sys are derived from f osc by the two divider stages, p-divider and k-divider. the system clock f sys can be equal to f cpu or f cpu /2. ? pll mode: in pll mode, the pll is running. the vco clock f vco is derived from f osc , divided by the p factor, multiplied by the pll (n-divider). the clock signals f cpu and f sys are derived from f vco by the k-divider. the system clock f sys can be equal to f cpu or f cpu /2. ? pll base mode: in pll base mode, the pll is running at its vco base frequency and f cpu and f sys www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 functional description data sheet 77 v1.0, 2008-04 are derived from f vco only by the k-divider. in this mode, the system clock f sys can be equal to f cpu or f cpu /2. figure 19 clock generation unit recommended oscillator circuits the oscillator circuit, a pierce oscillator, is designed to work with both, an external crystal oscillator or an external stable clock source. it basically consists of an inverting amplifier and a feedback element with xtal1 as input, and xtal2 as output. when using a crystal, a proper external oscillator circuitr y must be connected to both pins, xtal1 and xtal2. the crystal frequency can be within the range of 4 mhz to 25 mhz. additionally are necessary, two load capacitances c x1 and c x2 , and depending on the crystal type a series resistor r x2 to limit the current. a test resistor r q may be temporarily inserted to measure the oscillation allowance (negative resistance) of the oscillator circuitry. r q values are typically specified by the crystal vendor. the c x1 and c x2 values shown in figure 20 can be used as starting points for the negative resistance evaluation and for non-productive systems. the exact values and related operating range are dependent on the crystal frequency and have to be determined and mcb05600 phase detect. vco n- divider pll kdiv bypass p 5.3 / t xd1a main osc. circuit xtal1 x tal2 osc. run detect. f vco f n 1 f p m u x p- divider pll lock detect. clock output control f osc k- divider f cp u f sy s clock generation unit (cgu) vcosel vcobyp sysfs byppin ndiv lock oscdsic pdiv oscr ogc mosc oscillator control register osc_con pll clock control and status register pll_clc ordres system control unit (scu) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 functional description data sheet 78 v1.0, 2008-04 optimized together with the crystal vendor using the negative resistance method. oscillation measurement with the final target system is strongly recommended to verify the input amplitude at xtal1 and to determine the actual oscillation allowance (margin negative resistance) for the oscillator-crystal system. when using an external clock signal, it must be connected to xtal1. xtal2 is left open (unconnected). the external clock frequency can be in the range of 0 - 40 mhz if the pll is bypassed and 4 - 40 mhz if the pll is used. the oscillator can also be used in combination with a ceramic resonator. the final circuitry must be also verified by the resonator vendor. figure 20 shows the recommended external oscillator circuitries for both operating modes, external crystal mode and external input clock mode. figure 20 oscillator circuitries a block capacitor between v ddosc 1) / v ddosc3 and v ssosc is recommended, too. note: for crystal operation, it is strongly recommended to measure the negative resistance in the final target system (layout) to determine the optimum parameters 1) v ddosc and v ssosc are not bonded externally in the bc and bd steps of TC1796. an option for bonding them in future steps and products is kept open. mcs05601 TC1796 oscillator v ddosc v ssosc c x1 4 - 25 mhz c x2 xtal1 xtal2 TC1796 oscillator v ddosc v ssosc xtal1 xtal2 external clock signal f osc f osc fundamental mode crystal 4 1) - 40 mhz 1) in case of pll bypass 0 mhz v ddosc3 v ddosc3 crystal frequency c x1 , c x2 1) 4 mhz 8 mhz 12 mhz 16 - 25 mhz 10 pf 12 pf 18 pf 33 pf 1) note that these are evaluation start values! r x2 1) 0 0 0 0 r x2 r q www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 functional description data sheet 79 v1.0, 2008-04 for the oscillator operation. please refer to the minimum and maximum values of the negative resistance specified by the crystal supplier. 3.24 power supply the TC1796 has several power supply lines for different voltage classes: ?1.5 v: core logic and memory, oscillator, and a/d converter supply ?3.3 v: i/o ports, flash memories, oscillator, and a/d converter supply with reference voltages ?2.3 v to 3.3 v: external bus interface supply figure 21 shows the power supply concept of the TC1796 with the power supply pins and its connections to the functional units. figure 21 power supply concept of TC1796 TC1796 TC1796_pwrsupply v faref (3.3 v) v fagnd osc v ddmf (3.3 v) v ssmf v ddaf (1.5 v) v ssaf v ddm (3.3 v) v ssm v aref0 (3.3 v) v agnd0 v aref1 (3.3 v) v agnd1 v ddp (3.3 v) v ddebu (2.3 - 3.3 v) v dd (1.5 v) v ddsbram (1.5 v) v ddf l3 (3.3 v) v ddo sc (1.5 v) v ddo sc3 (3.3 v) v ssosc pll flash memories stand-by sbram pmi/pmu dmi/dmu memories ebu ports core adc0 adc1 fadc 2 2 2 2 2 2 v ss 62 11 9 13 1 2 3 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 functional description data sheet 80 v1.0, 2008-04 3.25 identification register values the identification registers uniquely identify a module or the whole device. table 9 TC1796 identification registers short name address value stepping scu_id f000 0008 h 002c c002 h ? manid f000 0070 h 0000 1820 h ? chipid f000 0074 h 0000 8a02 h ? rtid f000 0078 h 0000 0000 h ba-step 0000 0001 h bb-step 0000 0100 h bc-step 0000 0101 h bd-step 0000 0300 h be-step sbcu_id f000 0108 h 0000 6a0a h ? stm_id f000 0208 h 0000 c006 h ? cbs_jpdid f000 0408 h 0000 6307 h ? msc0_id f000 0808 h 0028 c002 h ? msc1_id f000 0908 h 0028 c002 h ? asc0_id f000 0a08 h 0000 4402 h ? asc1_id f000 0b08 h 0000 4402 h ? gpta0_id f000 1808 h 0029 c003 h ba-, bb-step 0029 c004 h bc-, bd-, be-step gpta1_id f000 2008 h 0029 c003 h ba-, bb-step 0029 c004 h bc-, bd-, be-step ltca2_id f000 2808 h 002a c003 h ba-, bb-step 002a c004 h bc-, bd-, be-step dma_id f000 3c08 h 001a c002 h ? can_id f000 4008 h 002b c002 h ? pcp_id f004 3f08 h 0020 c003 h ? rbcu_id f010 0008 h 0000 6a0a h ? ssc0_id f010 0108 h 0000 4530 h ? ssc1_id f010 0208 h 0000 4510 h ? fadc_id f010 0308 h 0027 c002 h ? www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 functional description data sheet 81 v1.0, 2008-04 adc0_id f010 0408 h 0030 c002 h ? mli0_id f010 c008 h 0025 c005 h ? mli1_id f010 c108 h 0025 c005 h ? mchk_id f010 c208 h 001b c001 h ? cps_id f7e0 ff08 h 0015 c006 h ? cpu_id f7e1 fe18 h 000a c005 h ? ebu_id f800 0008 h 0014 c005 h ? pmu_id f800 0508 h 002e c002 h ? flash_id f800 2008 h 0031 c002 h ? dmu_id f801 0108 h 002d c002 h ? dbcu_id f87f fa08 h 000f c005 h ? dmi_id f87f fc08 h 0008 c004 h ? pmi_id f87f fd08 h 000b c004 h ? lfi_id f87f ff08 h 000c c005 h ? pbcu_id f87f fe08 h 000f c005 h ? table 9 TC1796 identification registers (cont?d) short name address value stepping www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 electrical parameters data sheet 82 v1.0, 2008-04 4 electrical parameters 4.1 general parameters 4.1.1 parameter interpretation the parameters listed in this section partly represent the characteristics of the TC1796 and partly its requirements on the system. to aid interpreting the parameters easily when evaluating them for a design, they are marked with an two-letter abbreviation in column ?symbol?: ? cc such parameters indicate c ontroller c haracteristics which are a distinctive feature of the TC1796 and must be regarded for a system design. ? sr such parameters indicate s ystem r equirements which must provided by the microcontroller system in which the TC1796 designed in. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 electrical parameters data sheet 83 v1.0, 2008-04 4.1.2 pad driver and pad classes summary this section gives an overview on the different pad driver classes and its basic characteristics. more details (mainly dc parameters) are defined in the section 4.2.1 . table 10 pad driver and pad classes overview class power supply type sub class speed grade load leakage 1) 1) values are for t jmax = 150 c. termination a 3.3v lvttl i/o, lvttl output a1 (e.g. gpio) 6 mhz 100 pf 500 na no a2 (e.g. serial i/os) 40 mhz 50 pf 6 a series termination recommended a3 (e.g. trace outputs, serial i/os) 75 mhz 50 pf 6 a series termination recommended (for f > 25 mhz) a4 (e.g. trace clock) 150 mhz 25 pf 6 a series termination recommended b 2.375 - 3.6v 2) 2) ac characteristics for ebu pins are valid for 2.5 v 5% and 3.3 v 5%. lvttl i/o b1 (e.g. external bus interface) 40 mhz 50 pf 6 a no b2 (e.g. bus clock) 75 mhz 35 pf series termination recommended (for f > 25 mhz) c 3.3v lvds ? 50 mhz ? parallel termination 3) , 100 ? 10% 3) in applications where the lvds pins are not used (disabled), these pins must be either left unconnected, or properly terminated with the differential parallel termination of 100 ? 10%. d ? analog inputs, reference voltage inputs www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 electrical parameters data sheet 84 v1.0, 2008-04 4.1.3 absolute maximum ratings stresses above those listed under ?absol ute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. during absolute maximum rating overload conditions ( v in > related v dd or v in < v ss ) the voltage on the related v dd pins with respect to ground ( v ss ) must not exceed the values defined by the absolute maximum ratings. table 11 absolute maximum rating parameters parameter symbol values unit note / test con dition min. typ. max. ambient temperature t a sr -40 ? 125 c under bias storage temperature t st sr -65 ? 150 c ? junction temperature t j sr -40 ? 150 c under bias voltage at 1.5 v power supply pins with respect to v ss 1) 1) applicable for v dd , v ddsbram , v ddosc , v ddpll , and v ddaf . v dd sr ? ? 2.25 v ? voltage at 3.3 v power supply pins with respect to v ss 2) 2) applicable for v ddp , v ddebu , v ddfl3, v ddm , and v ddmf . v ddebu v ddp sr ? ? 3.75 v ? voltage on any class a input pin and dedicated input pins with respect to v ss v in sr -0.5 ? v ddp + 0.5 or max. 3.7 v whatever is lower voltage on any class b input pin with respect to v ss v in sr -0.5 ? v ddebu + 0.5 or max. 3.7 v whatever is lower voltage on any class d analog input pin with respect to v agnd v ain v arefx sr -0.5 ? v ddm + 0.5 or max. 3.7 v whatever is lower voltage on any class d analog input pin with respect to v ssaf v ainf v faref sr -0.5 ? v ddmf + 0.5 or max. 3.7 v whatever is lower cpu & lmb bus frequency f cpu sr ? ? 150 3) 3) the pll jitter characteristics add to this value according to the application settings. see the pll jitter parameters. mhz ? fpi bus frequency f sys sr ? ? 75 3) mhz ? www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 electrical parameters data sheet 85 v1.0, 2008-04 4.1.4 operating conditions the following operating conditions must not be exceeded in order to ensure correct operation of the TC1796. all parameters specif ied in the following table refer to these operating conditions, unless otherwise noticed. the following operating conditions must not be exceeded in order to ensure correct operation of the TC1796. all parameters specif ied in the following table refer to these operating conditions, unless otherwise noted. table 12 operating condition parameters parameter symbol values unit note / test condition min. typ. max. digital supply voltage 1) v dd sr v ddosc 2) sr 1.42 ? 1.58 3) v ? v ddp sr v ddosc3 sr 3.13 ? 3.47 4) v for class a pins (3.3v 5%) v ddebu sr 2.375 ? 3.47 4) v for class b (ebu) pins v ddfl3 sr 3.13 ? 3.47 4) v ? v ddsbram 5) sr 1.42 ? 1.58 3) v ? voltage on v ddsbram power supply pin to ensure data retention v dr sr 1.0 ? ? v 6) digital ground voltage v ss sr 0 ? ? v ? ambient temperature under bias t a sr ? -40 +125 c ? analog supply voltages ? ? ? ? ? see separate specification page 92 , page 99 cpu clock f cpu sr ? 7) ? 150 8) mhz ? short circuit current i sc sr -5 ? +5 ma 9) absolute sum of short circuit currents of a pin group (see table 13 ) | i sc | sr ? ? 20 ma see note 10) inactive device pin current i id sr -1 ? 1 ma voltage on all power supply pins v ddx = 0 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 electrical parameters data sheet 86 v1.0, 2008-04 absolute sum of short circuit currents of the device | i sc | sr ? ? 100 ma see note 10) external load capacitance c l sr ? ? ? pf depending on pin class. see dc characteristics 1) digital supply voltages applied to the TC1796 must be static regulated voltages which allow a typical voltage swing of 5%. 2) v ddosc and v ssosc are not bonded externally in the bc and bd steps of TC1796. an option for bonding them in future steps and products is kept open. 3) voltage overshoot up to 1.7 v is permissible at power-up and porst low, provided the pulse duration is less than 100 s and the cumulated summary of the pulses does not exceed 1 h. 4) voltage overshoot to 4 v is permissible at power-up and porst low, provided the pulse duration is less than 100 s and the cumulated summary of the pulses does not exceed 1 h 5) the v ddsb must be properly connected and supplied with power. if not, the TC1796 will not operate. in case of a stand-by operation, the core voltage must not float, but must be pulled low, in order to avoid internal cross- currents. 6) this applies only during power down state. during normal sram operation regular v dd has to be applied. 7) the TC1796 uses a static design, so the minimum operation frequency is 0 mhz. due to test time restriction no lower frequency boundary is tested, however. 8) the pll jitter characteristics add to this value according to the application settings. see the pll jitter parameters. 9) applicable for digital outputs. 10) see additional document ?TC1796 pin reliability in overload? for overload current definitions. table 13 pin groups for overload/short-circuit current sum parameter group pins 1 p4.[7:0] 2 p4.[14:8] 3 p4.15, slso[1:0], sclk0, mtsr0, mrst0, slsi0 4 wait , hold , bc[3:0] , hlda , mr/ w , baa , cscomb 5 cs[3:0] , rd , rd/ wr , breq , adv , bfclko 6 bfclki, d[31:24] 7 d[23:16] 8 d[15:8] table 12 operating condition parameters parameter symbol values unit note / test condition min. typ. max. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 electrical parameters data sheet 87 v1.0, 2008-04 9 d[7:0] 10 a[23:16] 11 a[15:8] 12 a[7:0] 13 tstres, tdi, tms, tck, trst , tdo, brkout , brkin , testmode 14 p10.[3:0], bypass, nmi , porst , hdrst 15 p9.[8:0] 16 fclp[1:0]a, fcln[1:0], sop[1:0]a, son[1:0] 17 p5.[7:0] 18 p3.[7:0] 19 p3.[15:8] 20 p0.[7:0] 21 p0.[15:8] 22 p2.[15:7] 23 p2.[6:2], p6.9, p6.8, p6.6, p6.11 24 p6.[15:12], p6.10, p6.7, p6.[5:4] 25 p8.[7:0] 26 p1.[15:13], p1.[11:8], p1.5 27 p1.12, p1.[7:6], p1.[4:0] 28 tr[15:8] 29 tr[7:1], trclk 30 tr0, p7.[7:0] table 13 pin groups for overload/short-circuit current sum parameter group pins www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 electrical parameters data sheet 88 v1.0, 2008-04 4.2 dc parameters 4.2.1 input/output pins table 14 input/output dc-characteristics (operating conditions apply) parameter symbol values unit note / test condition min. typ. max. general parameters pull-up current 1) | i puh | cc 10 ? 100 a v in < v ihamin ; class a1/a2/input pads. 20 ? 200 a v in < v ihamin ; class a3/a4 pads. 5 ? 85 a v in < v ihbmin ; class b1/b2 pads. pull-down current 1) | i pdl | cc 10 ? 150 a v in > v ilamax ; class a1/a2/input pads. v in > v ilbmax ; class b1/b2 pads 20 ? 200 a v in > v ilamax ; class a3/a4 pads. pin capacitance 1) (digital i/o) c io cc ? ? 10 pf f = 1 mhz t a = 25 c input only pads ( v ddp = 3.13 to 3.47 v = 3.3 v 5%) input low voltage class a1/a2 pins v ila sr -0.3 ? 0.34 v ddp v ? input high voltage class a1/a2 pins v iha sr 0.64 v ddp ? v ddp + 0.3 or max. 3.6 v whatever is lower ratio v il / v ih cc 0.53 ? ? ? ? input hysteresis hysa cc 0.1 v ddp ? ? v 5) 2) input leakage current i ozi cc ? ? 3000 6000 na v ddp /2-1 < v in < v ddp /2+1 otherwise 3) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 electrical parameters data sheet 89 v1.0, 2008-04 class a pads ( v ddp = 3.13 to 3.47 v = 3.3v 5%) output low voltage 4) v ola cc ? ? 0.4 v i ol = 2 ma for strong driver mode, i ol = 1.8 ma for medium driver mode, a2 pads i ol = 1.4 ma for medium driver mode, a1 pads i ol = 370 a for weak driver mode output high voltage 3) v oha cc 2.4 ? ? v i oh = -2 ma for strong driver mode, i oh = -1.8 ma for medium driver mode, a1/a2 pads i oh = -370 a for weak driver mode v ddp - 0.4 ? ? v i oh = -1.4 ma for strong driver mode, i oh = -1 ma for medium driver mode, a1/a2 pads i oh = -280 a for weak driver mode input low voltage class a1/2 pins v ila sr -0.3 ? 0.34 v ddp v ? input high voltage class a1/2 pins v iha sr 0.64 v ddp ? v ddp + 0.3 or 3.6 v whatever is lower ratio v il / v ih cc 0.53 ? ? ? ? input hysteresis hysa cc 0.1 v ddp ? ? v 5) 2) input leakage current class a2/3/4 pins i oza24 ? ? 3000 6000 na v ddp /2-1 < v in < v ddp /2+1 otherwise 3) input leakage current class a1 pins i oza1 cc ? ? 500 na 0 v < v in < v ddp table 14 input/output dc-characteristics (cont?d)(operating conditions apply) parameter symbol values unit note / test condition min. typ. max. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 electrical parameters data sheet 90 v1.0, 2008-04 class b pads ( v ddebu = 2.375 to 3.47 v) output low voltage v olb cc ? ? 0.4 v i ol = 2 ma output high voltage v ohb cc v ddebu - 0.4 ? ? v i ol = 2 ma input low voltage v ilb sr ? -0.3 0.34 v ddebu v ? input high voltage v ihb sr 0.64 v ddebu ? v ddebu +0.3 or 3.6 v whatever is lower ratio v il / v ih cc 0.53 ? ? ? ? input hysteresis hysb cc 0.1 v ddebu ? ? v 5) input leakage current class b pins i ozb cc ? ? 3000 6000 na v ddebu /2-0.6 < v in < v ddebu /2+0.6 6) otherwise 3) class c pads ( v ddp = 3.13 to 3.47 v = 3.3v 5%) output low voltage v ol cc 815 ? mv parallel termination 100 ? 1% output high voltage v oh cc ? 1545 mv parallel termination 100 ? 1% output differential voltage v od cc 150 ? 600 mv parallel termination 100 ? 1% output offset voltage v os cc 1075 ? 1325 mv parallel termination 100 ? 1% output impedance r 0 cc 40 ? 140 ? ? class d pads see adc characteristics ? ? ? ? ? 1) not subject to production test, verified by design / characterization. 2) the pads that have spike-filter function in the input path: porst , hdrst , nmi, do not have hysteresis. 3) only one of these parameters is tested, the other is verified by design characterization 4) max. resistance between pin and next power supply pin 25 ? for strong driver mode (verified by design characterization). table 14 input/output dc-characteristics (cont?d)(operating conditions apply) parameter symbol values unit note / test condition min. typ. max. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 electrical parameters data sheet 91 v1.0, 2008-04 5) function verified by design, value verified by design characterization. hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. it cannot be guaranteed that it suppresse s switching due to external system noise. 6) v ddebu = 2.5 v 5%. for v ddebu = 3.3 5% see class a2 pads. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 electrical parameters data sheet 92 v1.0, 2008-04 4.2.2 analog to digital converters (adc0/adc1) table 15 adc characteristics (operating conditions apply) parameter symbol values unit note / test condition min. typ. max. analog supply voltage v ddm sr 3.13 3.3 3.47 1) v ? v dd sr 1.42 1.5 1.58 2) v power supply for adc digital part, internal supply analog ground voltage v ssm sr -0.1 ? 0.1 v ? analog reference voltage 17) v arefx sr v agndx +1v v ddm v ddm + 0.05 1) 3)4) v ? analog reference ground 17) v agndx sr v ssmx - 0.05v 0 v aref - 1v v ? analog input voltage range v ain sr v agndx ? v arefx v ? analog reference voltage range 5) 17) v arefx - v agndx sr v ddm /2 ? v ddm + 0.05 v ? v ddm supply current i ddm sr ? 2.5 4 ma rms for each module 6) power-up calibration time t puc cc ? ? 3840 f adc clk ? internal adc clocks f bc cc 2 ? 40 mhz f bc = f ana 4 f ana cc 0.5 ? 10 mhz f ana = f bc / 4 total unadjusted error 5) tue 7) cc ? ? 1 lsb 8-bit conversion. ? ? 2 lsb 10-bit conversion ? ? 4 lsb 12-bit conversion 8)9) ? ? 8 lsb 12-bit conversion 10) 9) dnl error 11) 5) tue dnl cc ? 1.5 3.0 lsb 12-bit conversion 12) 9) inl error 11) 5) tue inl cc ? 1.5 3.0 lsb 12-bit conversion 12) 9) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 electrical parameters data sheet 93 v1.0, 2008-04 gain error 11) 5) tue gain cc ? 0.5 3.5 lsb 12-bit conversion 12) 9) offset error 11) 5) tue off cc ? 1.0 4.0 lsb 12-bit conversion 12) 9) input leakage current at analog inputs an0, an1, an4 to an7, an24 to an31. see figure 24 13) 14) i oz1 cc -1000 ? 300 na (0% v ddm ) < v in < (2% v ddm ) -200 ? 400 na (2% v ddm ) < v in < (95% v ddm ) -200 ? 1000 na (95% v ddm ) < v in < (98% v ddm ) -200 ? 3000 na (98% v ddm ) < v in < (100% v ddm ) input leakage current at the other analog inputs, that is an2, an3, an8 to an23, an32 to an43 see figure 24 14) i oz1 cc -1000 ? 200 na (0% v ddm ) < v in < (2% v ddm ) -200 ? 300 na (2% v ddm ) < v in < (95% v ddm ) -200 ? 1000 na (95% v ddm ) < v in < (98% v ddm ) -200 ? 3000 na (98% v ddm ) < v in < (100% v ddm ) input leakage current at v aref i oz2 cc ? ? 1 a 0 v < v aref < v ddm, no conversion running input current at v aref0/1 17) i aref cc ? 35 75 a rms 0 v < v aref < v ddm 15) total capacitance of the voltage reference inputs 16)17) c areftot cc ? ? 25 pf 9) switched capacitance at the positive reference voltage input 17) c arefsw cc ? 15 20 pf 9) 18) table 15 adc characteristics (cont?d) (operating conditions apply) parameter symbol values unit note / test condition min. typ. max. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 electrical parameters data sheet 94 v1.0, 2008-04 resistance of the reference voltage input path 16) r aref cc ? 1 1.5 k ? 500 ohm increased for an[1:0] used as reference input 9) total capacitance of the analog inputs 16) c aintot cc ? ? 25 pf 6) 9) switched capacitance at the analog voltage inputs c ainsw cc ? ? 7 pf 9) 19) on resistance of the transmission gates in the analog voltage path r ain cc ? 1 1.5 k ? 9) on resistance for the adc test (pull- down for ain7) r ain7t cc 200 300 1000 ? test feature available only for ain7 9) current through resistance for the adc test (pull- down for ain7) i ain7t cc ? 15 rms 30 peak ma test feature available only for ain7 9) 1) voltage overshoot to 4 v are permissible, provided the pulse duration is less than 100 s and the cumulated summary of the pulses does not exceed 1 h. 2) voltage overshoot to 1.7 v are permissible, provided the pulse duration is less than 100 s and the cumulated summary of the pulses does not exceed 1 h. 3) a running conversion may become inexact in case of violating the normal operating conditions (voltage overshoot). 4) if the reference voltage v aref increases or the v ddm decreases, so that v aref = ( v ddm + 0.05v to v ddm + 0.07v), then the accuracy of the adc decreases by 4lsb12. 5) if a reduced reference voltage in a range of v ddm /2 to v ddm is used, then the adc converter errors increase. if the reference voltage is reduced with the factor k (k<1), then tue, dnl, inl gain and offset errors increase with the factor 1/k. if a reduced reference voltage in a range of 1 v to v ddm /2 is used, then there are additional decrease in the adc speed and accuracy. 6) current peaks of up to 6 ma with a duration of max. 2 ns may occur 7) tue is tested at v aref = 3.3 v, v agnd = 0 v and v ddm = 3.3 v table 15 adc characteristics (cont?d) (operating conditions apply) parameter symbol values unit note / test condition min. typ. max. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 electrical parameters data sheet 95 v1.0, 2008-04 8) adc module capability. 9) not subject to production test, verified by design / characterization. 10) value under typical application conditions due to integration (switching noise, etc.). 11) the sum of dnl/inl/gain/offset errors does not exceed the related tue total unadjusted error. 12) for 10-bit conversions the dnl/inl/gain/offset error values must be multiplied with factor 0.25. for 8-bit conversions the dnl/inl/gain/offset error values must be multiplied with 0.0625. 13) the leakage current definition is a continuous function, as shown in figure 24 . the numerical values defined determine the characteristic points of the given continuous linear approximation - they do not define step function. 14) only one of these parameters is tested, the other is verified by design characterization. 15) i aref_max is valid for the minimum specified conversion time. the current flowing during an adc conversion with a duration of up to t c = 25s can be calculated with the formula i aref_max = q conv / t c . every conversion needs a total charge of q conv = 150pc from v aref . all adc conversions with a duration longer than t c = 25s consume an i aref_max = 6a. 16) for the definition of the parameters see also figure 23 . 17) applies to ain0 and ain1, when used as auxiliary reference inputs. 18) this represents an equivalent switched capacitance. this capacitance is not switched to the reference voltage at once. instead of this smaller capacitances ar e successively switched to the reference voltage. 19) the sampling capacity of the conversion c-network is pre-charged to v aref /2 before the sampling moment. because of the parasitic elements the voltage measured at ainx is lower then v aref /2, typically 0.85v. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 electrical parameters data sheet 96 v1.0, 2008-04 figure 22 adc0/adc1 clock circuit table 16 sample and conversion time (operating conditions apply) parameter symbol values unit note min. typ. max. sample time t s cc 4 (chconn.stc + 2) t bc s ? 8 t bc ? ? s ? conversion time t c cc t s + 40 t bc + 2 t div s 8-bit conversion t s + 48 t bc + 2 t div s 10-bit conversion t s + 56 t bc + 2 t div s 12-bit conversion mca04657_mod programmable clock divider (1:1) to (1:256) f bc f di v fractional divider f clc f ana programmable counter sample time t s con.ctc chconn.stc f timer control/status logic interrupt logic external trigger logic external multiplexer logic request generation logic a/d converter module arbiter (1:20) control unit (timer) 1:4 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 electrical parameters data sheet 97 v1.0, 2008-04 figure 23 adc0/adc1 input circuits reference voltage input circuitry analog input circuitry analog_inprefdiag r ext = v ain c ext r ain, on c aintot - c ainsw c ainsw anx v aref r aref, on c areftot - c arefsw c arefsw v agndx v arefx r ain7t v agndx www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 electrical parameters data sheet 98 v1.0, 2008-04 figure 24 adc0/adc1analog inputs leakage others v in [ v ddm %] 300na 1ua 3ua 2% 95% 100% 98% i oz1 an0, an1, an4 - an7, an24 - an31 v in [ v ddm %] 400na -1ua 3ua 2% 95% 100% 98% i oz1 300na -200na 200na 1ua -1ua -200na adc leakage 7.vsd www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 electrical parameters data sheet 99 v1.0, 2008-04 4.2.3 fast analog to digital converter (fadc) table 17 fadc characteristics (operating conditions apply) parameter symbol values unit note / test condition min. typ. max. dnl error e dnl cc ? ? 1 lsb 10) inl error e inl cc ? ? 4 lsb 10) gradient error 1) 10) e grad cc ? ? 3 % with calibration, gain 1, 2 2) e grad cc ? ? 5 % without calibration gain 1, 2, 4 e grad cc ? ? 6 % without calibration gain 8 offset error 10) e off 3) cc ? ? 20 4) mv with calibration 2) ? ? 60 4) mv without calibration reference error of internal v faref /2 e ref cc ? ? 60 mv ? analog supply voltages v ddmf sr 3.13 ? 3.47 5) v ? v ddaf sr 1.42 ? 1.58 6) v ? analog ground voltage v ssaf sr -0.1 ? 0.1 v ? analog reference voltage v faref sr 3.13 ? 3.47 5) 7) v nominal 3.3 v analog reference ground v fagnd sr v ssaf - 0.05v ? v ssaf +0.05v v ? analog input voltage range v ainf sr v fagnd ? v ddmf v ? analog supply currents i ddmf sr ? ? 9 ma ? i ddaf sr ? ? 17 ma 8) input current at each v faref i faref cc ? ? 150 a rms independent of conversion input leakage current at v faref 9) i foz2 cc ? ? 500 na 0 v < v in < v ddmf input leakage current at v fagnd i foz3 cc ? ? 8 a 0 v < v in < v ddmf www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 electrical parameters data sheet 100 v1.0, 2008-04 the calibration procedure should run after each power-up, when all power supply voltages and the reference voltage have stabilized. the offset calibration must run first, followed by the gain calibration. conversion time t c cc ? ? 21 clk of f adc 10-bit conversion converter clock f adc cc ? ? 75 mhz ? input resistance of the analog voltage path (rn, rp) r fain cc 100 ? 200 k ? 10) channel amplifier cutoff frequency f coff cc 2 ? ? mhz ? settling time of a channel amplifier after changing enn or enp t set cc ? ? 5 sec ? 1) calibration of the gain is possible for the gain of 1 and 2, and not possible for the gain of 4 and 8. 2) calibration should be performed at each power-up. in case of continuous operation, calibration should be performed minimum once per week. 3) the offset error voltage drifts over the whole temperature range maximum 3 lsb. 4) applies when the gain of the channel equals one. for the other gain settings, the offset error increases; it must be multiplied with the applied gain. 5) voltage overshoot to 4 v are permissible, provided the pulse duration is less than 100 s and the cumulated summary of the pulses does not exceed 1 h. 6) voltage overshoot to 1.7 v are permissible, provided the pulse duration is less than 100 s and the cumulated sum of the pulses does not exceed 1 h. 7) a running conversion may become inexact in case of violating the normal operating conditions (voltage overshoots). 8) current peaks of up to 40 ma with a duration of max. 2 ns may occur 9) this value applies in power-down mode. 10) not subject to production test, verified by design / characterization. table 17 fadc characteristics (operating conditions apply) (cont?d) parameter symbol values unit note / test condition min. typ. max. www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 electrical parameters data sheet 101 v1.0, 2008-04 figure 25 fadc input circuits fadc_inprefdiag = + - + - r n fainxn fainxp v fagnd fadc analog input stage r p v faref /2 v faref fadc reference voltage input circuitry v fagnd v faref i faref www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 electrical parameters data sheet 102 v1.0, 2008-04 4.2.4 oscillator pins note: it is strongly recommended to measure the oscillation allowance (negative resistance) in the final target system (layout) to determine the optimal parameters for the oscillator operation. please refer to the limits specified by the crystal supplier. table 18 oscillator pins characteristics (operating conditions apply) parameter symbol values unit note / test condition min. typ. max. frequency range f osc cc 4 ? 25 mhz ? input low voltage at xtal1 1) 1) if the xtal1 pin is driven by a crystal, reaching a minimum amplitude (peak-to-peak) of 0.3 v ddosc3 is necessary. v ilx sr -0.2 ? 0.3 v ddosc3 v ? input high voltage at xtal1 1) v ihx sr 0.7 v ddosc3 ? v ddosc3 + 0.2 v ? input current at xtal1 i ix1 cc ? ? 25 a 0 v < v in < v ddosc3 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 electrical parameters data sheet 103 v1.0, 2008-04 4.2.5 temperature sensor table 19 temperature sensor characteristics (operating conditions apply) parameter symbol values unit note / test cond ition min. typ. max. temperature sensor range t sr sr -40 150 c ? start-up time after resets inactive t tsst sr ? ? 10 s ? sensor inaccuracy t tsa cc ? ? 10 c ? a/d converter clock for dts signal f ana sr ? ? 10 mhz conversion with adc1 table 20 temperature sensor characteristics (operating conditions apply) parameter symbol typical value unit note temperature of the die at the sensor location t ts cc t ts = (adc_code - 487) 0.396 - 40 c 10-bit adc result t ts = (adc_code - 1948) 0.099 - 40 c 12-bit adc result www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 electrical parameters data sheet 104 v1.0, 2008-04 4.2.6 power supply current ??? table 21 power supply currents (operating conditions apply) parameter symbol values unit note / test condition min. typ. max. porst low current at v dd i dd_porst cc ? ? 300 ma the pll running at the base frequency porst low current at v ddp , and porst high current without any port activity i ddp_porst cc ? ? 25 ma the pll running at the base frequency active mode core supply current 1)2) 1) infineon power loop: cpu and pcp running, all peripherals active. the power consumption of each custom application will most probably be lower than this value, but must be evaluated separately. 2) the i dd decreases for typically 120 ma if the f cpu is decreased for 50 mhz, at constant t j = 150c, for the infineon max power loop. the dependency in this range is, at constant junction temperature, linear. i dd cc 10 ? 700 ma f cpu =150mhz f cpu / f sys = 2:1 active mode analog supply current i ddax; i ddmx cc ? ? ? ma see adc0/1 fadc stand-by ram supply current in stand-by i sbsb cc ? ? 9 ma v ddsb = 1v, t j = 150 o c oscillator and pll core power supply i ddosc 3) cc 3) v ddosc and v ssosc are not bonded externally in the bc and bd steps of TC1796. an option for bonding them in future steps and products is kept open. ? ? 5 ma ? oscillator and pll pads power supply i ddosc3 cc ? ? 3.6 ma ? lvds port supply (via v ddp ) 4) 4) in case the lvds pads are disabled, the power consumption pro pair is negligible (less than 1 a). i lvds cc ? ? 50 ma lvds pads active flash power supply current i ddfl3 cc ? ? 80 ma ? maximum allowed power dissipation 5) 5) for the calculation of junction to ambient thermal resistance r tja , see page 130 . p d sr ? ? p d r tja < 25 o c ? worst case t a = 125 o c www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 electrical parameters data sheet 105 v1.0, 2008-04 4.3 ac parameters all ac parameters are defined with the temperature compensation disabled. that means, keeping the pads constantly at maximum strength. 4.3.1 testing waveforms figure 26 rise/fall time parameters figure 27 testing waveform, output delay figure 28 testing waveform, output high impedance 10% 90% 10% 90% v ss v ddebu v ddp t r rise_fall t f mct04881_a.vsd v dde / 2 test points v dde / 2 v ss v ddebu v ddp mct04880_new v load + 0.1 v v oh - 0.1 v timing reference points v load - 0.1 v v ol - 0.1 v www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 electrical parameters data sheet 106 v1.0, 2008-04 4.3.2 output rise/fall times table 22 output rise/fall times (operating conditions apply) parameter symbol values unit note / test condition min. typ. max. class a1 pads rise/fall times 1) 1) not all parameters are subject to production test, but verified by design/characterization and test correlation. t ra1 , t fa1 ? ? 50 140 18000 150 550 65000 ns regular (medium) driver, 50 pf regular (medium) driver, 150 pf regular (medium) driver, 20 nf weak driver, 20 pf weak driver, 150 pf weak driver, 20 000 pf class a2 pads rise/fall times 1) t ra2 , t fa2 ? ? 3.3 6 5.5 16 50 140 18000 150 550 65000 ns strong driver, sharp edge, 50 pf strong driver, sharp edge, 100pf strong driver, medium edge, 50 pf strong driver, soft edge, 50 pf medium driver, 50 pf medium driver, 150 pf medium driver, 20 000 pf weak driver, 20 pf weak driver, 150 pf weak driver, 20 000 pf class a3 pads rise/fall times 1) t ra3 , t fa3 ? ? 2.5 ns 50 pf class a4 pads rise/fall times 1) t ra3 , t fa3 ? ? 2.0 ns 25 pf class b pads rise/fall times 1) 2) t rb , t fb ? ? 3.0 4.0 7.0 ns 35 pf 50 pf 100 pf class c pads rise/fall times t rc , t fc ? ? 2 ns ? www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 electrical parameters data sheet 107 v1.0, 2008-04 4.3.3 power sequencing there is a restriction for the power sequencing of the 3.3 v domain including v ddebu as shown in figure 29 : it must always be higher than 1.5 v domain - 0.5 v. the grey area shows the valid range for v 3.3v and v ddebu relative to an exemplary 1.5 v ramp. v ddp , v ddosc3 , v ddfl3 , v ddm , v ddmf belong to the 3.3 v power supply domain, that is referenced in figure 29 as v 3.3 . the v ddm and v ddmf sub domains are connected with anti parallel esd protection diodes in TC1796 design steps bc and bd. the v ddm , v ddmf , v ddp , v ddosc3 sub domains are connected with anti parallel esd protection diodes in TC1796 design step be. v dd , v ddosc and v ddaf belong to the 1.5 v power supply domain, referenced as v 1.5 . v ddebu belongs to its own 2.5v to 3.3v domain. figure 29 v ddp / v ddebu / v dd power up sequence all ground pins v ss must be externally connected to one single star point in the system. the difference voltage between the ground pins must not exceed 200 mv. the porst signal must be activated at latest before any power supply voltage falls below the levels shown on the figure below. in this case, only the memory row of a flash memory that was a target of a write at the moment of the power loss will contain unreliable content. additionally, the porst signal should be activated as soon as possible. the sooner the porst signal is activated, the less time the system operates outside of the normal operating power supply range. 2) parameter test correlation for v ddebu = 2.5 v 5% powerseq 2 v 1.5 v 3.3 , v ddebu v 3.3 , v ddebu > v 1.5 - 0.5v time v a l i d a r e a f o r v 3 . 3 a n d v d d e b u v a l i d a r e a f o r v 3 . 3 a n d v d d e b u time v ddp (3.3v) porst 3.3v 1.5v www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 electrical parameters data sheet 108 v1.0, 2008-04 figure 30 power down / power loss sequence powerdown3.3_1.5_reset_only.vsd v ddp , v ddebu, v ddfl3 power supply voltage t porst v porst3.3 v ddp -5% -12% 3.3v 3.13v 2.9v v ddpmin t t porst t v dd -5% -12% 1.5v 1.42v 1.32v v dd v porst1.5min v ddmin www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 electrical parameters data sheet 109 v1.0, 2008-04 4.3.4 power, pad and reset timing table 23 power, pad and reset timing parameters parameter symbol values unit note / test con dition min. typ. max. min. v ddp voltage to ensure defined pad states 1) v ddppa cc 0.6 ? ? v ? oscillator start-up time 2) t oscs cc ? ? 10 ms ? minimum porst active time after power supplies are stable at operating levels t poa sr 10 ? ? ms ? hdrst pulse width t hd cc 1024 clock cycles 3) 6) ? ? f sys ? porst rise time t por sr ? ? 50 ms ? setup time to porst rising edge 4) t pos sr 0 ? ? ns ? hold time from porst rising edge 4) t poh sr 100 ? ? ns ? setup time to hdrst rising edge 5) t hds sr 0 ? ? ns ? hold time from hdrst rising edge 5) t hdh sr 100 + (2 1/ f sys ) 6) ? ? ns ? ports inactive after porst reset active 7)8) t pip cc ? ? 150 ns ? ports inactive after hdrst reset active t pi cc ? ? 150 + 5 1/ f sys ns ? minimum v ddp porst activation threshold 9) v porst3.3 sr ? ? 2.9 v ? minimum v dd porst activation threshold 9) v porst1.5 sr ? ? 1.32 v ? power on reset boot time 9) t bp cc ? ? 2 ms ? hardware/software reset boot time at f cpu =150mhz 10) t b cc 150 ? 350 s ? www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 electrical parameters data sheet 110 v1.0, 2008-04 1) this parameter is valid under assumption that porst signal is constantly at low level during the power- up/power-down of the v ddp . 2) t oscs is defined from the moment when v ddosc3 = 3.13v until the oscillations reach an amplitude at xtal1 of 0,3* v ddosc3 . this parameter is verified by device characterization. the external oscillator circuitry must be optimized by the customer and checked for negative resistance as recommended and specified by crystal suppliers. 3) any hdrst activation is internally prolonged to 1024 fpi bus clock ( f sys ) cycles. 4) applicable for input pins testmode , trst , brkin , and txd1a with noise suppression filter of porst switched-on (bypass = 0). 5) the setup/hold values are applicable for port 0 and port 10 input pins with noise suppression filter of hdrst switched-on (bypass = 0), independently whether hdrst is used as input or output. 6) f sys = f cpu /2 7) not subject to production test, verified by design / characterization. 8) this parameter includes the delay of the analog spike filter in the porst pad. 9) the duration of the boot-time is defined between the rising edge of the porst and the moment when the first user instruction has entered the cpu and its processing starts. 10) the duration of the boot time is defined between the following events: 1. hardware reset: the falling edge of a short hdrst pulse and the moment when the first user instruction has entered the cpu and its processing starts, if the hdrst pulse is shorter than 1024 t sys . if the hdrst pulse is longer than 1024 t sys , only the time beyond the 1024 t sys should be added to the boot time ( hdrst falling edge to first user instruction). 2. software reset: the moment of starting the software reset and the moment when the first user instruction has entered the cpu and its processing starts www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 electrical parameters data sheet 111 v1.0, 2008-04 figure 31 power, pad and reset timing reset_beh1 1) as programmed v ddp porst hdrst pads pad- state undefined t pi v dd v ddppa v ddppa pad- state undefined 2) tri-state, pull device active t hd v ddpr osc 1) 2) 1) 2) 2) t poa t poa t hd t oscs www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 electrical parameters data sheet 112 v1.0, 2008-04 4.3.5 phase locked loop (pll) note: all pll characteristics defined on this and the next page are verified by design characterization. phase locked loop operation when pll operation is enabled and configured, the pll clock f vco (and with it the cpu clock f cpu ) is constantly adjusted to the selected frequency. the relation between f vco and f sys is defined by: f vco = k f cpu . the pll causes a jitter of f cpu and affects the clock outputs bfclko, trclk, and sysclk (p1.12) which are derived from the pll clock f vco . there will be defined two formulas that define the (absolute) approximate maximum value of jitter d p in ns dependent on the k-factor, the cpu clock frequency f cpu in mhz, and the number p of consecutive f cpu clock periods. (1) (2) table 24 pll parameters (operating conditions apply) parameter symbol values unit note / test con dition min. typ. max. accumulated jitter d p see figure 3 2 ? ? ? ? vco frequency range f vco 400 ? 500 mhz ? 600 ? 700 mhz ? 500 ? 600 mhz ? pll base frequency 1) 1) the cpu base frequency which is selected after reset is calculated by dividing the limit values by 16 (this is the k factor after reset). f pllbase 140 ? 320 mhz ? 150 ? 400 mhz ? 200 ? 480 mhz ? pll lock-in time t l ? ? 200 s ? p k 385 < d pns [] 7000 p f cpu 2 mhz [] k ------------------------------------------ - 0 535 , + = p k 385 d pns [] 2700000 f cpu 2 mhz [] k 2 --------------------------------------------- 0 5 3 5 , + = www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 electrical parameters data sheet 113 v1.0, 2008-04 note: the frequency of system clock f sys can be selected to be either f cpu or f cpu /2. with rising number p of clock cycles the maximum jitter increases linearly up to a value of p that is defined by the k-factor of the pll. beyond this value of p the maximum accumulated jitter remains at a constant value. further, a lower cpu clock frequency f cpu results in a higher absolute maximum jitter value. figure 32 gives the jitter curves for several k/ f cpu combinations. figure 32 approximated maximum accumulated pll jitter for typical cpu clock frequencies f cpu (overview) 0 0.0 p ns d p 4.0 8.0 12.0 20.0 20 40 60 80 100 120 16.0 o tc1976_pll_jitt f cpu = 50 mhz ( k = 8) f cpu = 100 mhz ( k = 4) f cpu = 120 mhz ( k = 4) f cpu = 150 mhz ( k = 4) f cpu = 100 mhz ( k = 7) f cpu = 50 mhz ( k = 14) = max. jitter = number of consecutive f cpu periods = k-divider of pll d p p k o www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 electrical parameters data sheet 114 v1.0, 2008-04 figure 33 approximated maximum accumulated pll jitter for typical cpu clock frequencies f cpu (detail) note: the specified pll jitter values are valid if the capacitive load at the external bus unit (ebu) is limited to c l =20pf. note: the maximum peak-to-peak noise on the core supply voltage (measured between v dd at pin e23 and v ss at pin d23, or adjacent supply pairs) is limited to a peak-to-peak voltage of v pp = 30mv. this condition can be achieved by appropriate blocking of the core supply voltage as near as possible to the supply pins and using pcb supply and ground planes.=20pf. 0 0.0 p ns d p 0.5 1.0 2.5 4.0 24 68 10 14 3.5 20 d p p k = max. jitter = number of consecutive f cpu periods = k-divider of pll tc1976_pll_detail f cpu = 50 mhz ( k = 8) 3.0 1.5 2.0 16 12 18 f cpu = 50 mhz ( k = 14) f cpu = 100 mhz ( k = 4) f cpu = 150 mhz ( k = 4) f cpu = 100 mhz ( k = 7) www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 electrical parameters data sheet 115 v1.0, 2008-04 4.3.6 bfclko output clock timing v ss = 0 v; v dd = 1.5 v 5%; v ddebu = 2.5 v 5% and 3.3 v 5%; t a = -40 c to +125 c; c l = 35 pf figure 34 bfclko output clock timing table 25 bfclk0 output clock timing parameters 1) 1) not subject to production test, verified by design/characterization. parameter symbol values unit note / test con dition min. typ. max. bfclko clock period t bfclko cc 13.33 2) 2) the pll jitter characteristics add to this value according to the application settings. see the pll jitter parameters. ? ? ns ? bfclko high time t 5 cc 3 ? ? ns ? bfclko low time t 6 cc 3 ? ? ns ? bfclko rise time t 7 cc ? ? 3 ns ? bfclko fall time t 8 cc ? ? 3 ns ? bfclko duty cycle t 5 /( t 5 + t 6 ) 3) 3) the pll jitter is not included in this parameter. if the bfclko frequency is equal to f cpu , the k-divider setting determines the duty cycle. dc24 cc 45 50 55 % divider of 2, 4, ... 4) 4) the division ratio between lmb and bfclko frequency is set by ebu_bfcon.extclock. bfclko duty cycle t 5 /( t 5 + t 6 ) 3) dc3 cc 30 33.33 36 % divider of 3 4) bfclko high time reduction 5) 5) due to asymmetry of the delays and slopes of the rising and falling edge of the pad. the influence of the pll jitter is included in this parameter. this parameter should be applied taking the typical value of the duty cycle in the account, not the minimum or maximum value. dt 5 cc ? ? 1.1 ns c l = 20pf 0.9 v dd mct04883_mod 0.5 v ddp05 bfclko t bfclko t 5 t 6 0.1 v dd t 8 t 7 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 electrical parameters data sheet 116 v1.0, 2008-04 bfclk timing and pll jitter the bfclk timing is important for calculating the timing of an external flash memory. in principle bfclk timing can be derived from the pll jitter formulas. in case of only ebu synchronous read access to the flash device the worst case jitter is partially lower. for one bfclk with a cycle time of 13,33 ns the maximum jitter is t jpp = |+/-620 ps| for two bfclks with an accumulated cycle time of 26,66 ns the maximum jitter is t jpacc = |+/- 660 ps| www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 electrical parameters data sheet 117 v1.0, 2008-04 4.3.7 debug trace timing v ss = 0 v; v ddp = 3.13 to 3.47 v (class a); t a = -40 c to +125 c; c l (trclk) = 25 pf; c l (tr[15:0]) = 50 pf; figure 35 debug trace timing table 26 debug trace timing parameter 1) 1) not subject to production test, verified by design/characterization. parameter symbol values unit note / test con dition min. typ. max. tr[15:0] new state from trclk rising edge t 9 cc -1 ? 4 ns ? trace_tmg trclk t 9 tr[15:0] old state new state www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 electrical parameters data sheet 118 v1.0, 2008-04 4.3.8 jtag interface timing operating conditions apply, cl = 50 pf figure 36 tck clock timing table 27 tck clock timing parameter parameter symbol values unit note / test con dition min. typ. max. tck clock period 1) 1) f tck should be lower or equal to f sys . t tck sr 25 ? ? ns ? tck high time t 1 sr 10 ? ? ns ? tck low time t 2 sr 10 ? ? ns ? tck clock rise time t 3 sr ? ? 4 ns ? tck clock fall time t 4 sr ? ? 4 ns ? 0.9 v dd jtag_tck 0.5 v ddp tck t tck t 1 t 2 0.1 v dd t 4 t 3 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 electrical parameters data sheet 119 v1.0, 2008-04 figure 37 jtag timing note: the jtag module is fully compliant with ieee1149.1-2000 with jtag clock at 20 mhz. the jtag clock at 40mhz is possible with the modified timing diagram shown in figure 37 . table 28 jtag timing parameters 1) 1) f tck should be lower or equal to f sys . parameter symbol values unit note / test con dition min. typ. max. tms setup to tck rising edge t 1 sr 6.0 ? ? ns ? tms hold to tck rising edge t 2 sr 6.0 ? ? ns ? tdi setup to tck rising edge t 1 sr 6.0 ? ? ns ? tdi hold to tck rising edge t 2 sr 6.0 ? ? ns ? tdo valid output from tck falling edge 2) 2) the falling edge on tck is used to capture the tdo timing. t 3 cc ? ? 13 ns c l = 50 pf t 3 cc 3.0 ? ? ns c l = 20 pf tdo high impedance to valid output from tck falling edge 2) t 4 cc ? ? 14 ns c l = 50 pf tdo valid output to high impedance from tck falling edge 2) t 5 cc ? ? 13.5 ns c l = 50 pf t 1 t 2 t 1 t 2 t 4 t 3 t 5 jtag tck tms tdi tdo www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 electrical parameters data sheet 120 v1.0, 2008-04 4.3.9 ebu demultiplexed timing v ss = 0 v; v dd = 1.5 v 5%; v ddebu = 2.5 v 5% and 3.3 v 5%, class b pins; t a = -40 c to +125 c; c l = 35 pf; table 29 ebu demultiplexed timing parameters 1) 1) not subject to production test, verified by design/characterization. parameter symbol values unit note / test con dition min. typ. max. output delay from bfclko rising edge 2) 2) valid for bfcon.extclock = 00 b . t 10 cc 0 ? 5 ns ? rd active/inactive after bfclko rising edge 2) t 12 cc 0 ? 3 ns ? data setup to bfclko rising edge 2) t 13 sr 8.5 ? ? ns ? data hold from bfclko rising edge 2) t 14 sr 0 ? ? ns ? wait setup (low or high) to bfclko rising edge 2) t 15 sr 3 ? ? ns ? wait hold (low or high) from bfclko rising edge 2) t 16 sr 2 ? ? ns ? data hold after rd/ wr rising edge t 17 sr 0 ? ? ns ? www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 electrical parameters data sheet 121 v1.0, 2008-04 4.3.9.1 demultiplexed read timing figure 38 ebu demultiplexed read timing inval. address demuxrd_1.vsd t 10 bfclko a[23:0] t 10 adv t 10 address phase command del. phase (opt.) command phase recovery phase (opt.) new addr. phase t 10 t 10 t 10 cs[3:0] cscomb t 10 t 10 valid address next addr. rd rd/wr mr/w d[31:0] bc[3:0] wait t 12 t 12 valid data t 13 t 14 t 10 t 10 t 10 t 10 t 16 t 15 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 electrical parameters data sheet 122 v1.0, 2008-04 4.3.9.2 demultiplexed write timing figure 39 ebu demultiplexed write timing inval. address demuxwr_1.vsd t 10 bfclko a[23:0] t 10 adv t 10 address phase command del. phase (opt.) command phase recovery phase (opt.) new addr. phase t 10 t 10 t 10 t 10 t 10 valid address next addr. rd rd/wr mr/w d[31:0] bc[3:0] wait t 10 t 10 data out t 10 t 10 t 10 data hold phase t 10 t 10 t 10 t 10 t 10 t 10 t 16 t 15 t 17 cs[3:0] cscomb www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 electrical parameters data sheet 123 v1.0, 2008-04 4.3.10 ebu burst mode read timing v ss = 0 v; v dd = 1.5 v 5%; v ddebu = 2.5 v 5% and 3.3 v 5%, class b pins; t a = -40 c to +125 c; c l = 35 pf; table 30 ebu burst mode read timing parameters 1) 1) not subject to production test, verified by design/characterization. parameter symbol values unit note / test con dition min. typ. max. output delay from bfclko rising edge t 10 cc 0 ? 5 ns ? rd active/inactive after bfclko rising edge t 12 cc 0 ? 5 ns ? cs x output delay from bfclko rising edge t 21 cc 0 ? 4 ns ? adv / baa active/inactive after bfclko rising edge 2) 2) this parameter is valid for bfcon.ebse0 = 1 (or bfcon.ebse1 = 1). note that t 22 is increased by: 1/2 of the lmb bus clock period t cpu = 1/ f cpu when bfcon.ebse0 = 0 (or bfcon.ebse1 = 0). t 22 cc 0 ? 4 ns ? data setup to bfclki rising edge t 23 sr 3 ? ? ns ? data hold from bfclki rising edge t 24 sr 0 ? ? ns ? wait setup (low or high) to bfclki rising edge t 25 sr 3 ? ? ns ? wait hold (low or high) from bfclki rising edge t 26 sr 2 ? ? ns ? www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 electrical parameters data sheet 124 v1.0, 2008-04 figure 40 ebu burst mode read timing data (addr+4) burstrd_4. vsd t 10 bfclki bfclko a[23:0] t 22 adv t 10 address phase(s) command phase(s) burst phase(s) recovery phase(s) next addr. phase(s) t 22 t 10 t 10 burst start address next addr. rd d[31:0] (32-bit) wait t 12 t 12 data (addr+0) t 24 baa d[15:0] (16-bit) t 22 burst phase(s) data (addr+2) data (addr+0) t 22 t 10 t 22 t 23 t 24 t 23 1) t 26 t 25 output delays are always referenced to bclko. the reference clock for input characteristics depends on bit ebu_bfcon.fdbken. ebu_bfcon.fdbken = 0:bfclko is the input reference clock. ebu_bfcon.fdbken = 1:bfclki is the input reference clock (ebu clock feedback enabled). 1) cs[3:0] cscomb www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 electrical parameters data sheet 125 v1.0, 2008-04 4.3.11 ebu arbitration signal timing v ss = 0 v; v dd = 1.5 v 5%; v ddebu = 2.5 v 5% and 3.3 v 5%, class b pins; t a = -40 c to +125 c; c l = 35 pf; figure 41 ebu arbitration signal timing table 31 ebu arbitration signal timing parameters 1) 1) not subject to production test, verified by design/characterization. parameter symbol values unit note / test con dition min. typ. max. output delay from clkout rising edge t 27 cc ? ? 3 ns ? data setup to clkout falling edge t 28 sr 8 ? ? ns ? data hold from clkout falling edge t 29 sr 2 ? ? ns ? ebuarb_1 bfclko hlda output breq output t 27 t 27 t 27 t 27 t 29 t 28 t 29 t 28 bfclko hold inp ut hlda input www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 electrical parameters data sheet 126 v1.0, 2008-04 4.3.12 peripheral timings note: peripheral timing parameters are not su bject to production test. they are verified by design/characterization. 4.3.12.1 micro link interface (mli) timing table 32 mli timing parameters (operating conditions apply), c l = 50 pf parameter symbol values unit note / test con dition min. typ. max. tclk clock period 1)2) 1) tclk signal rise/fall times are the same as the a2 pads rise/fall times. 2) tclk high and low times can be minimum 1 t mli. t 30 cc 2 3) 3) when f sys = 75 mhz, t 30 = 26,67ns ? ? 1 / f sys ? rclk clock period t 31 sr 1 ? ? 1 / f sys ? mli outputs delay from tclk rising edge t 35 cc 0 ? 8 ns ? mli inputs setup to rclk falling edge t 36 sr 4 ? ? ns ? mli inputs hold to rclk falling edge t 37 sr 4 ? ? ns ? rready output delay from rclk falling edge t 38 cc 0 ? 8 ns ? www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 electrical parameters data sheet 127 v1.0, 2008-04 figure 42 mli interface timing note: the generation of rreadyx is in the input clock domain of the receiver. the reception of treadyx is asynchronous to tclkx. mli_tmg_2.vsd tdatax tvalidx t 35 t 35 t 37 t 36 tclkx 0.1 v ddp 0.9 v ddp rdatax rvalidx rclkx t 31 treadyx rreadyx t 38 t 38 t 30 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 electrical parameters data sheet 128 v1.0, 2008-04 4.3.12.2 micro second channel (msc) interface timing figure 43 msc interface timing note: the data at sop should be sampled with the falling edge of fclp in the target device. table 33 msc interface timing (operating conditions apply), c l = 50 pf parameter symbol values unit note / test con dition min. typ. max. fclp clock period 1)2) 1) fclp signal rise/fall times are the same as the a2 pads rise/fall times. 2) fclp signal high and low can be minimum 1 t msc . t 40 cc 2 t msc 3) 3) t mscmin = t sys = 1/ f sys . when f sys = 75 mhz, t 40 = 26,67ns ? ? ns ? sop/enx outputs delay from fclp rising edge t 45 cc -10 10 ns ? sdi bit time t 46 cc 8 t msc ? ns ? sdi rise time t 48 sr 100 ns ? sdi fall time t 49 sr 100 ns ? msc_tmg_1.vsd t 45 t 45 t 40 0.1 v ddp 0.9 v ddp t 46 t 48 0.1 v ddp 0.9 v ddp t 49 t 46 sop en fclp sdi www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 electrical parameters data sheet 129 v1.0, 2008-04 4.3.12.3 synchronous serial channel (ssc) master mode timing figure 44 ssc master mode timing table 34 ssc master mode timing (operating conditions apply), c l = 50 pf parameter symbol values unit note / test con dition min. typ. max. sclk clock period 1)2) 1) sclk signal rise/fall times are the same as the a2 pads rise/fall times. 2) sclk signal high and low times can be minimum 1 t ssc . t 50 cc 2 t ssc 3) 3) t sscmin = t sys = 1/ f sys . when f sys = 75 mhz, t 50 = 26,67ns ? ? ns ? mtsr/slsox delay from sclk rising edge t 51 cc 0 ? 8 ns ? mrst setup to sclk falling edge t 52 sr 10 ? ? ns ? mrst hold from sclk falling edge t 53 sr 5 ? ? ns ? ssc_tmg_1.vsd sclk 1)2) mtsr 1) t 51 t 51 mrst 1) t 53 data valid t 52 slsox 2) t 51 1) this timing is based on the following setup: con.ph = con.po = 0. 2) the transition at slsox is based on the following setup: ssotc.trail = 0 and the first sclk high pulse is in the first one of a transmission. t 50 www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 package and reliability data sheet 130 v1.0, 2008-04 5 package and reliability 5.1 package parameters (p/pg-bga-416-4) table 35 thermal characteristics of the package parameter symbol values unit note / test condi tion min. typ. max. thermal resistance junction case top 1) 1) the top and bottom thermal resistances between the case and the ambient ( r tcat , r tcab ) are to be combined with the thermal resistances between the junction and the case given above ( r tjct , r tjcb ), in order to calculate the total thermal resistance between the junction and the ambient ( r tja ). the thermal resistances between the case and the ambient ( r tcat , r tcab ) depend on the external system (pcb, case) characteristics, and are under user responsibility. the junction temperature can be calculated using the following equation: t j = t a + r tja p d , where the r tja is the total thermal resistance between the junction and the ambient. this total junction ambient resistance r tja can be obtained from the upper four partial thermal resistances. r tjct cc ? 8 k/w ? thermal resistance junction case bottom 1) r tjcb cc ? 15 k/w ? www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 package and reliability data sheet 131 v1.0, 2008-04 5.2 package outline figure 45 p/pg-bga-416-4, plastic low profile pitch ball grid array you can find our packages, sorts of packing and others in our infineon internet web site. gpa09537 a26 2.5 max. index marking (sharp edge) index marking af1 a1 25 x 1 = 25 25 x 1 = 25 1 1 (1.17) (0.56) 0.1 0.5 m c ?0.1 ?0.63 -0.13 +0.07 a 416x ?0.25 m b c 0.15 c a 0.2 20 0.5 24 0.2 27 0.2 0.5 0.2 27 20 24 b www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 package and reliability data sheet 132 v1.0, 2008-04 5.3 flash memory parameters the data retention time of the TC1796?s flash memory (i.e. the time after which stored data can still be retrieved) depends on the number of times the flash memory has been erased and programmed. table 36 flash parameters parameter symbol values unit note / test condition min. typ. max. program / data flash retention time, physical sector 1)2) 1) storage and inactive time included. 2) at average weighted junction temperature t j = 100 o c, or the retention time at average weighted temperature of t j = 110 o c is minimum 10 years, or the retention time at average weighted temperature of t j = 150 o c is minimum 0.7 years. t ret cc 20 ? ? years max. 1000 erase/program cycles program / data flash retention time logical sector 1) 2) t retl cc 20 ? ? years max. 100 erase/program cycles data flash endurance (128 kb) n e cc 15 000 ? ? ? max. data retention time 5 years data flash endurance, eeprom emulation (8 16 kb) n e8 cc 120 000 ? ? ? max. data retention time 5 years programming time per page 3) 3) in case the program verify feature detects weak bits, these bits will be programmed once more. the reprogramming takes additional 5 ms. t pr cc ? ? 5 ms ? program flash erase time per 256-kb sector t erp cc ? ? 5 s f cpu = 150 mhz data flash erase time per 64-kb sector t erd cc ? ? 2.5 s f cpu = 150 mhz wake-up time t wu cc 4300 1/ f cpu + 40 s ? ? ? ? www.datasheet.co.kr datasheet pdf - http://www..net/ TC1796 package and reliability data sheet 133 v1.0, 2008-04 5.4 quality declarations table 37 quality parameters parameter symbol values unit note / test condition min. typ. max. operation lifetime 1)2) 1) this lifetime refers only to the time when the device is powered on. 2) one example of a detailed temperature profile is: 2000 hours at t j = 150 o c 16000 hours at t j = 125 o c 6000 hours at t j = 110 o c this example is equivalent to the operation lifetime and average temperatures given in the table. t op ? ? 24000 hours at average weighted junction temperature t j = 127 o c ? ? 66000 hours at average weighted junction temperature t j = 100 o c ? ? 20 years at average weighted junction temperature t j = 85 o c esd susceptibility according to human body model (hbm) v hbm ? ? 2000 v conforming to eia/jesd22-a114-b esd susceptibility of the lvds pins v hbm1 ? ? 500 v ? esd susceptibility according to charged device model (cdm) v cdm ? ? 500 v conforming to jesd22-c101-c moisture sensitivity level msl ? ? 3 ? conforming to jedec j-std-020c for 240c www.datasheet.co.kr datasheet pdf - http://www..net/ www.infineon.com published by infineon technologies ag www.datasheet.co.kr datasheet pdf - http://www..net/ |
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